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1. 发明授权

US08042260B2 Methods of forming inductors on integrated circuits 有权
标题翻译：在集成电路上形成电感器的方法
公开(公告)号：US08042260B2
公开(公告)日：2011-10-25
申请号：US12250385
申请日：2008-10-13
申请人： Peter J. Hopper , Peter Johnson , Peter Smeys , Andrei Papou
发明人： Peter J. Hopper , Peter Johnson , Peter Smeys , Andrei Papou
IPC分类号： H01F7/06
CPC分类号： H01L23/5227 , H01F17/0006 , H01F41/046 , H01L2924/0002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49075 , Y10T29/49124 , Y10T29/4913 , H01L2924/00
摘要： The claimed invention pertains to methods of forming one or more inductors on a semiconductor substrate. In one embodiment, a method of forming an array of inductor core elements on a semiconductor substrate that includes integrated circuits is disclosed. A first set of spaced apart metallic core elements are formed over the substrate. Isolation sidewalls are then formed on side surfaces of the core elements. Afterward, a second set of metallic core elements are formed over the substrate. The first and second sets of core elements are substantially co-planar and interleaved such that only the isolation sidewalls separate adjacent core elements. Particular embodiments involve other processing operations, such as the selective electroplating of different types of metal to form core elements and/or the deposition and etching away of an isolation layer to form isolation sidewalls on the core elements.
摘要翻译：所要求保护的发明涉及在半导体衬底上形成一个或多个电感器的方法。在一个实施例中，公开了一种在包括集成电路的半导体衬底上形成电感器芯元件阵列的方法。第一组间隔开的金属芯元件形成在衬底上。然后在芯元件的侧表面上形成隔离侧壁。之后，在衬底上形成第二组金属芯元件。第一和第二组芯元件基本上是共面的和交错的，使得只有隔离侧壁分隔相邻的芯元件。具体实施例涉及其他处理操作，例如不同类型的金属的选择性电镀以形成核心元件和/或沉积和蚀刻离开隔离层以在核心元件上形成隔离侧壁。

2. 发明授权

US07755463B2 Integrated circuits with inductors 有权
标题翻译：集成电路与电感器
公开(公告)号：US07755463B2
公开(公告)日：2010-07-13
申请号：US12250382
申请日：2008-10-13
申请人： Peter J. Hopper , Peter Johnson , Peter Smeys , Andrei Papou
发明人： Peter J. Hopper , Peter Johnson , Peter Smeys , Andrei Papou
IPC分类号： H01F5/00 , H01F27/28 , H01F21/06 , H01F27/30 , H01F27/24 , H02M1/00 , G05F1/00
CPC分类号： H01L23/5227 , H01F17/0006 , H01F41/046 , H01L2924/0002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49075 , Y10T29/49124 , Y10T29/4913 , H01L2924/00
摘要： The claimed invention relates to arrangements of inductors and integrated circuit dice. One embodiment pertains to an integrated circuit die that has an inductor formed thereon. The inductor includes an inductor winding having a winding input and a winding output. The inductor also comprises an inductor core array having at least first and second sets of inductor core elements that are magnetically coupled with the inductor winding. Each inductor core element in the first set of inductor core elements is formed from a first metallic material. Each inductor core element in the second set of inductor core elements is formed from a second metallic material that has a different magnetic coercivity than the first magnetic material. The inductor further comprises a set of spacers that electrically isolate the inductor core elements. Some embodiments involve multiple inductor windings and/or multiple inductor core elements that magnetically interact in various ways. Particular embodiments involve core elements having different compositions and/or sizes.
摘要翻译：所要求保护的发明涉及电感器和集成电路芯片的布置。一个实施例涉及其上形成有电感器的集成电路管芯。电感器包括具有绕组输入和绕组输出的电感器绕组。电感器还包括电感器芯阵列，其具有与电感器绕组磁耦合的至少第一组和第二组电感器芯体元件。第一组电感器芯元件中的每个电感器芯体元件由第一金属材料形成。第二组电感器芯元件中的每个电感器芯体元件由具有与第一磁性材料不同的磁矫顽力的第二金属材料形成。电感器还包括一组将电感器芯元件电隔离的间隔件。一些实施例涉及以各种方式磁性相互作用的多个电感器绕组和/或多个电感器核心元件。具体实施方案涉及具有不同组成和/或尺寸的核心元件。

3. 发明申请

US20090040000A1 INTEGRATED CIRCUITS WITH INDUCTORS 有权
标题翻译：集成电路与电感器
公开(公告)号：US20090040000A1
公开(公告)日：2009-02-12
申请号：US12250382
申请日：2008-10-13
申请人： Peter J. Hopper , Peter Johnson , Peter Smeys , Andrei Papou
发明人： Peter J. Hopper , Peter Johnson , Peter Smeys , Andrei Papou
IPC分类号： H01F5/00
CPC分类号： H01L23/5227 , H01F17/0006 , H01F41/046 , H01L2924/0002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49075 , Y10T29/49124 , Y10T29/4913 , H01L2924/00
摘要： The claimed invention relates to arrangements of inductors and integrated circuit dice. One embodiment pertains to an integrated circuit die that has an inductor formed thereon. The inductor includes an inductor winding having a winding input and a winding output. The inductor also comprises an inductor core array having at least first and second sets of inductor core elements that are magnetically coupled with the inductor winding. Each inductor core element in the first set of inductor core elements is formed from a first metallic material. Each inductor core element in the second set of inductor core elements is formed from a second metallic material that has a different magnetic coercivity than the first magnetic material. The inductor further comprises a set of spacers that electrically isolate the inductor core elements. Some embodiments involve multiple inductor windings and/or multiple inductor core elements that magnetically interact in various ways. Particular embodiments involve core elements having different compositions and/or sizes.
摘要翻译：所要求保护的发明涉及电感器和集成电路芯片的布置。一个实施例涉及其上形成有电感器的集成电路管芯。电感器包括具有绕组输入和绕组输出的电感器绕组。电感器还包括电感器芯阵列，其具有与电感器绕组磁耦合的至少第一组和第二组电感器芯体元件。第一组电感器芯元件中的每个电感器芯体元件由第一金属材料形成。第二组电感器芯元件中的每个电感器芯体元件由具有与第一磁性材料不同的磁矫顽力的第二金属材料形成。电感器还包括一组将电感器芯元件电隔离的间隔件。一些实施例涉及以各种方式磁性相互作用的多个电感器绕组和/或多个电感器核心元件。具体实施方案涉及具有不同组成和/或尺寸的核心元件。

4. 发明授权

US07468899B1 Apparatus and method for wafer level fabrication of high value inductors on semiconductor integrated circuits 有权
标题翻译：用于在半导体集成电路上制造高价值电感器的晶片级的装置和方法
公开(公告)号：US07468899B1
公开(公告)日：2008-12-23
申请号：US11621424
申请日：2007-01-09
申请人： Peter J. Hopper , Peter Johnson , Peter Smeys , Andrei Papou
发明人： Peter J. Hopper , Peter Johnson , Peter Smeys , Andrei Papou
IPC分类号： G05F1/59 , G05F1/618
CPC分类号： H01L23/5227 , H01F17/0006 , H01F41/046 , H01L2924/0002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49075 , Y10T29/49124 , Y10T29/4913 , H01L2924/00
摘要： An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits is disclosed. The integrated circuit includes a plurality of regulator circuits, each of the regulator circuits having an input node configured to receive a plurality of pulsed input signals having a predetermined duty cycle and a plurality of inductor windings associated with each of the plurality of regulator circuits respectively. The integrated circuit also includes a core array having a plurality of core elements. The plurality of core elements are positioned adjacent to and magnetically coupled with one or more of the plurality of inductor windings. An output node is electrically coupled to the plurality of inductor windings. The output signal at the output node is the sum of the instantaneous voltage on each of the inductor windings associated with the plurality of regulator circuits respectively. The integrated circuit also includes a phase control circuit coupled to the plurality of regulator circuits. The phase control circuit controls the phase of the plurality of pulsed input signals received at the plurality of the regulator circuits to control the output signal at the output node.
摘要翻译：公开了一种直接在半导体集成电路之上晶圆级制造高值电感器的装置和方法。集成电路包括多个调节器电路，每个调节器电路具有被配置为分别接收具有预定占空比的多个脉冲输入信号和与多个调节器电路中的每一个相关联的多个电感器绕组的输入节点。集成电路还包括具有多个核心元件的芯阵列。多个芯元件被定位成与多个电感器绕组中的一个或多个相邻并且磁耦合。输出节点电耦合到多个电感器绕组。输出节点处的输出信号分别是与多个调节器电路相关联的每个电感器绕组上的瞬时电压之和。集成电路还包括耦合到多个调节器电路的相位控制电路。相位控制电路控制在多个调节器电路处接收的多个脉冲输入信号的相位，以控制输出节点处的输出信号。

5. 发明授权

US07936246B2 On-chip inductor for high current applications 有权
标题翻译：用于大电流应用的片上电感
公开(公告)号：US07936246B2
公开(公告)日：2011-05-03
申请号：US11973536
申请日：2007-10-09
申请人： Peter J. Hopper , Peter Smeys , Andrei Papou
发明人： Peter J. Hopper , Peter Smeys , Andrei Papou
IPC分类号： H01F27/24
CPC分类号： H01F17/0013 , H01F3/14 , H01F27/34 , H01F41/046 , H01F2017/0066 , Y10T29/49078
摘要： Saturation of nonlinear ferromagnetic core material for on-chip inductors for high current applications is significantly reduced by providing a core design wherein magnetic flux does not form a closed loop, but rather splits into multiple sub-fluxes that are directed to cancel each other. The design enables high on-chip inductance for high current power applications.
摘要翻译：用于大电流应用的片上电感器的非线性铁磁芯材料的饱和度通过提供其中磁通量不形成闭环但是分成多个子通量的核心设计而显着降低，这些子通量被引导以相互抵消。该设计可实现高电流功率应用的高片内电感。

6. 发明授权

US08390093B1 System and method of galvanic isolation in digital signal transfer integrated circuits utilizing conductivity modulation of semiconductor substrate 有权
标题翻译：利用半导体衬底的电导率调制的数字信号传输集成电路中的电流隔离的系统和方法
公开(公告)号：US08390093B1
公开(公告)日：2013-03-05
申请号：US13230171
申请日：2011-09-12
申请人： Peter J. Hopper , Peter Smeys , William French , Andrei Papou , Aditi Dutt Chaudhuri
发明人： Peter J. Hopper , Peter Smeys , William French , Andrei Papou , Aditi Dutt Chaudhuri
IPC分类号： H01L21/70 , H01L21/00 , H04B1/44
CPC分类号： H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： A galvanic isolation system provides galvanic isolation in digital transfer integrated circuits by using conductivity modulation of the semiconductor substrate. Modulation of the conductivity of the substrate affects eddy current losses of a (differential) RF inductor that is isolated from the substrate by a sufficient amount of dielectric material, which provides a basis for signal transfer from the modulated substrate to the inductor across the isolation barrier.
摘要翻译：电隔离系统通过使用半导体衬底的电导率调制在数字传输集成电路中提供电隔离。衬底的导电性的调制影响了通过足够量的电介质材料与衬底隔离的（差分）RF电感器的涡电流损耗，这提供了通过隔离屏障从调制衬底到电感器的信号传递的基础。

7. 发明授权

US08338913B2 Semiconductor inductor with a serpentine shaped conductive wire interlaced with a serpentine shaped ferromagnetic core 有权
标题翻译：具有蛇形导电线的半导体电感器与蛇形铁磁芯线交织
公开(公告)号：US08338913B2
公开(公告)日：2012-12-25
申请号：US12943391
申请日：2010-11-10
申请人： Peter Smeys , Andrei Papou , Peter J. Hopper
发明人： Peter Smeys , Andrei Papou , Peter J. Hopper
IPC分类号： H01L29/82
CPC分类号： H01L28/10 , H01L23/5227 , H01L23/645 , H01L2924/0002 , H01L2924/00
摘要： The inductance of an inductor is increased by forming a conductive wire to have a serpentine shape that weaves through a ferromagnetic core that has a number of segments that are connected together in a serpentine shape where each segment of the ferromagnetic core also has a number of sections that are connected together in a serpentine shape.
摘要翻译：电感器的电感通过形成导线而增加，其具有蛇形形状，该蛇形形状通过铁磁芯编织，所述铁磁芯具有以蛇形形式连接在一起的多个段，其中铁磁芯的每个段也具有多个部分它们以蛇形形状连接在一起。

8. 发明申请

US20090160592A1 Helical core on-chip power inductor 审中-公开
标题翻译：螺旋内核功率电感
公开(公告)号：US20090160592A1
公开(公告)日：2009-06-25
申请号：US12004384
申请日：2007-12-20
申请人： Peter J. Hopper , Peter Smeys , Kyuwoon Hwang , Andrei Papou
发明人： Peter J. Hopper , Peter Smeys , Kyuwoon Hwang , Andrei Papou
IPC分类号： H01F27/02 , H01F41/00
CPC分类号： H01F17/04 , H01F3/06 , H01F3/14 , H01F17/0006 , H01F17/06 , H01F41/045 , H01F41/046 , H01L23/5227 , H01L2924/0002 , Y10T29/4902 , H01L2924/00
摘要： An on-chip inductor structure includes a conductive inductor coil and a helical ferromagnetic inductor core that is formed to wrap around the conductive coil. The coil is space-apart from the ferromagnetic core by intervening dielectric material. The helical core structure includes at least one magnetic gap lithographically formed in the core.
摘要翻译：片上电感器结构包括导电电感线圈和形成为缠绕导电线圈的螺旋铁磁电感器芯。线圈通过插入介电材料与铁磁芯隔开。螺旋芯结构包括至少一个在芯中光刻形成的磁隙。

9. 发明申请

US20130062725A1 SYSTEM AND METHOD OF GALVANIC ISOLATION IN DIGITAL SIGNAL TRANSFER INTEGRATED CIRCUITS UTILIZING CONDUCTIVITY MODULATION OF SEMICONDUCTOR SUBSTRATE 有权
标题翻译：使用半导体基板的电导率调制的数字信号传输集成电路中的电池隔离系统和方法
公开(公告)号：US20130062725A1
公开(公告)日：2013-03-14
申请号：US13230171
申请日：2011-09-12
申请人： Peter J. Hopper , Peter Smeys , William French , Andrei Papou , Chaudhuri Dutt Adilti
发明人： Peter J. Hopper , Peter Smeys , William French , Andrei Papou , Chaudhuri Dutt Adilti
IPC分类号： H01L29/02 , H01L21/02 , H01L21/31
CPC分类号： H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： A galvanic isolation system provides galvanic isolation in digital transfer integrated circuits by using conductivity modulation of the semiconductor substrate. Modulation of the conductivity of the substrate affects eddy current losses of a (differential) RF inductor that is isolated from the substrate by a sufficient amount of dielectric material, which provides a basis for signal transfer from the modulated substrate to the inductor across the isolation barrier.
摘要翻译：电隔离系统通过使用半导体衬底的电导率调制在数字传输集成电路中提供电隔离。衬底的导电性的调制影响了通过足够量的电介质材料与衬底隔离的（差分）RF电感器的涡电流损耗，这提供了通过隔离屏障从调制衬底到电感器的信号传递的基础。

10. 发明申请

US20120112296A1 Semiconductor Inductor with a Serpentine Shaped Conductive Wire and a Serpentine Shaped Ferromagnetic Core and a Method of Forming the Semiconductor Inductor 有权
标题翻译：具有蛇形导体线和蛇形铁磁铁芯的半导体电感器和形成半导体电感器的方法
公开(公告)号：US20120112296A1
公开(公告)日：2012-05-10
申请号：US12943391
申请日：2010-11-10
申请人： Peter Smeys , Andrei Papou , Peter J. Hopper
发明人： Peter Smeys , Andrei Papou , Peter J. Hopper
IPC分类号： H01L29/82 , H01L21/02
CPC分类号： H01L28/10 , H01L23/5227 , H01L23/645 , H01L2924/0002 , H01L2924/00
摘要： The inductance of an inductor is increased by forming a conductive wire to have a serpentine shape that weaves through a ferromagnetic core that has a number of segments that are connected together in a serpentine shape where each segment of the ferromagnetic core also has a number of sections that are connected together in a serpentine shape.
摘要翻译：电感器的电感通过形成导线而增加，其具有蛇形形状，该蛇形形状通过铁磁芯编织，所述铁磁芯具有以蛇形形式连接在一起的多个段，其中铁磁芯的每个段也具有多个部分它们以蛇形形状连接在一起。

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