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1. 发明申请

US20080283824A1 METHOD AND STRUCTURE FOR FORMING STRAINED SI FOR CMOS DEVICES 有权
标题翻译：用于形成CMOS器件的应变SI的方法和结构
公开(公告)号：US20080283824A1
公开(公告)日：2008-11-20
申请号：US12173642
申请日：2008-07-15
申请人： An L. STEEGEN , Haining S. Yang , Ying Zhang
发明人： An L. STEEGEN , Haining S. Yang , Ying Zhang
IPC分类号： H01L29/778
CPC分类号： H01L29/7833 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02658 , H01L21/26506 , H01L21/76224 , H01L21/76232 , H01L21/76283 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/1054 , H01L29/665 , H01L29/66575 , H01L29/78 , H01L29/7842 , H01L29/7846 , H01L29/7849
摘要： A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.
摘要翻译：半导体器件包括具有在半导体衬底的一部分下延伸的至少一个间隙的半导体衬底。栅极堆叠在半导体衬底上。应变层形成在至少一个间隙的至少一部分中。应变层仅形成在半导体器件的源极区域和漏极区域中的至少一个之下。

2. 发明申请

US20100109048A1 METHOD AND STRUCTURE FOR FORMING STRAINED SI FOR CMOS DEVICES 有权
标题翻译：用于形成CMOS器件的应变SI的方法和结构
公开(公告)号：US20100109048A1
公开(公告)日：2010-05-06
申请号：US12685054
申请日：2010-01-11
申请人： An L. STEEGEN , Haining S. YANG , Ying ZHANG
发明人： An L. STEEGEN , Haining S. YANG , Ying ZHANG
IPC分类号： H01L29/267 , H01L29/78
CPC分类号： H01L29/7833 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02658 , H01L21/26506 , H01L21/76224 , H01L21/76232 , H01L21/76283 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/1054 , H01L29/665 , H01L29/66575 , H01L29/78 , H01L29/7842 , H01L29/7846 , H01L29/7849
摘要： A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.
摘要翻译：半导体器件包括具有在半导体衬底的一部分下延伸的至少一个间隙的半导体衬底。栅极堆叠在半导体衬底上。应变层形成在至少一个间隙的至少一部分中。应变层仅形成在半导体器件的源极区域和漏极区域中的至少一个之下。

3. 发明授权

US07655557B2 CMOS silicide metal gate integration 失效
标题翻译： CMOS硅化物金属栅极集成
公开(公告)号：US07655557B2
公开(公告)日：2010-02-02
申请号：US12145113
申请日：2008-06-24
申请人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral, Jr. , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
发明人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral, Jr. , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
摘要翻译：本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

4. 发明授权

US07326983B2 Selective silicon-on-insulator isolation structure and method 有权
标题翻译：选择性绝缘体上硅绝缘体隔离结构及方法
公开(公告)号：US07326983B2
公开(公告)日：2008-02-05
申请号：US11082993
申请日：2005-03-17
申请人： An L. Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
发明人： An L. Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
IPC分类号： H01L27/108
CPC分类号： H01L29/66651 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0653 , H01L29/66772
摘要： A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.
摘要翻译：本发明的第一方面是一种形成隔离结构的方法，包括：（a）提供半导体衬底; （b）在衬底中形成掩埋的N掺杂区域; （c）在所述衬底中形成垂直沟槽，所述沟槽延伸到所述N掺杂区域中; （d）去除所述N掺杂区域以形成与所述垂直沟槽连通并垂直于所述垂直沟槽延伸的横向沟槽; 和（e）至少部分地填充横向沟槽并用一种或多种绝缘材料填充垂直沟槽。

5. 发明授权

US07129126B2 Method and structure for forming strained Si for CMOS devices 失效
标题翻译：用于形成CMOS器件的应变Si的方法和结构
公开(公告)号：US07129126B2
公开(公告)日：2006-10-31
申请号：US10605906
申请日：2003-11-05
申请人： An L. Steegen , Haining S. Yang , Ying Zhang
发明人： An L. Steegen , Haining S. Yang , Ying Zhang
IPC分类号： H01L21/8238
CPC分类号： H01L29/7833 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02658 , H01L21/26506 , H01L21/76224 , H01L21/76232 , H01L21/76283 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/1054 , H01L29/665 , H01L29/66575 , H01L29/78 , H01L29/7842 , H01L29/7846 , H01L29/7849
摘要： A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves doping a portion of a semiconductor substrate and forming a gap in the semiconductor substrate by removing at least a portion of the doped portion of the semiconductor substrate. The method further involves growing a strain layer in at least a portion of the gap in the semiconductor substrate. For the n-type device, the strain layer is grown on at least a portion which is substantially directly under a channel of the n-type device. For the p-type device, the strain layer is grown on at least a portion which is substantially directly under a source region or drain region of the p-type device and not substantially under a channel of the p-type device.
摘要翻译：一种制造包括n型器件和p型器件的器件的方法。在本发明的一个方面，该方法包括通过去除半导体衬底的掺杂部分的至少一部分来掺杂半导体衬底的一部分并在半导体衬底中形成间隙。该方法还包括在半导体衬底中的间隙的至少一部分中生长应变层。对于n型器件，应变层在基本上直接位于n型器件的沟道下方的至少一部分上生长。对于p型器件，应变层生长在基本上直接位于p型器件的源极区域或漏极区域的部分上，并且基本上不在p型器件的沟道下生长。

6. 发明授权

US07081397B2 Trench sidewall passivation for lateral RIE in a selective silicon-on-insulator process flow 失效
标题翻译：在选择性绝缘体上硅工艺流程中横向RIE的沟槽侧壁钝化
公开(公告)号：US07081397B2
公开(公告)日：2006-07-25
申请号：US10929990
申请日：2004-08-30
申请人： Christopher V. Baiocco , An L. Steegen , Ying Zhang
发明人： Christopher V. Baiocco , An L. Steegen , Ying Zhang
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A lateral trench in a semiconductor substrate is formed by the following steps. Form a lateral implant mask (LIM) over a top surface of the semiconductor substrate. Implant a heavy dopant concentration into the substrate through the LIM to form a lateral implant region (LIR) in the substrate. Strip the LIM exposing the top surface of the substrate. Form an epitaxial silicon layer over the top surface of the substrate burying the LIR. Form a trench mask over the epitaxial layer. Etch a trench reaching through the epitaxial layer and the LIR. Form oxidized trench sidewalls, an oxidized trench bottom and oxidized sidewalls of the LIR. Etch the oxidized sidewalls of the LIR until the LIR is exposed. Form laterally extending trenches by etching away the LIR.
摘要翻译：通过以下步骤形成半导体衬底中的横向沟槽。在半导体衬底的顶表面上形成横向植入掩模（LIM）。通过LIM将重掺杂浓度植入到衬底中，以在衬底中形成横向植入区域（LIR）。剥离LIM暴露衬底的顶部表面。在掩埋LIR的衬底的顶表面上形成外延硅层。在外延层上形成沟槽掩模。蚀刻穿过外延层和LIR的沟槽。形成氧化的沟槽侧壁，氧化沟槽底部和LIR的氧化侧壁。蚀刻LIR的氧化侧壁，直到LIR暴露。通过蚀刻掉LIR形成横向延伸的沟槽。

7. 发明授权

US06927117B2 Method for integration of silicide contacts and silicide gate metals 失效
标题翻译：硅化物触点和硅化物栅极金属的集成方法
公开(公告)号：US06927117B2
公开(公告)日：2005-08-09
申请号：US10725851
申请日：2003-12-02
申请人： Cyril Cabral, Jr. , Jakub T. Kedzierski , Victor Ku , Christian Lavoie , Vijay Narayanan , An L. Steegen
发明人： Cyril Cabral, Jr. , Jakub T. Kedzierski , Victor Ku , Christian Lavoie , Vijay Narayanan , An L. Steegen
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L21/823835
摘要： A CMOS silicide metal integration scheme that allows for the incorporation of silicide contacts (S/D and gates) and metal silicide gates using a self-aligned process (salicide) as well as one or more lithography steps is provided. The integration scheme of the present invention minimizes the complexity and cost associated with fabricating a CMOS structure containing silicide contacts and silicide gate metals.
摘要翻译：提供了允许使用自对准工艺（自对准硅化物）以及一个或多个光刻步骤并入硅化物触点（S / D和栅极）和金属硅化物栅极的CMOS硅化物金属集成方案。本发明的集成方案使与制造包含硅化物触点和硅化物栅极金属的CMOS结构相关联的复杂性和成本最小化。

8. 发明授权

US06869866B1 Silicide proximity structures for CMOS device performance improvements 失效
标题翻译：用于CMOS器件性能改进的硅化物接近结构
公开(公告)号：US06869866B1
公开(公告)日：2005-03-22
申请号：US10605310
申请日：2003-09-22
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Rajesh Rengarajan , An L. Steegen
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Rajesh Rengarajan , An L. Steegen
IPC分类号： H01L21/28 , H01L21/336 , H01L21/38 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/45 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/823807 , H01L21/823864 , H01L21/84 , H01L27/1203 , H01L29/458 , H01L29/7842 , H01L29/7845 , H01L29/78654
摘要： A method for manufacturing an integrated circuit having a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor on a semiconductor wafer by creating a spacer having a first width for the n-type field effect transistor and creating a spacer having a second width for the p-type field effect transistor, the first width being greater than the second width and depositing silicide material on the semiconductor wafer such that tensile mechanical stresses are formed within a channel of the n-type field effect transistor and compressive stresses are formed within a channel of the p-type field effect transistor.
摘要翻译：一种制造集成电路的方法，该集成电路具有在半导体晶片上具有n型场效应晶体管和p型场效应晶体管的多个半导体器件，该半导体器件具有用于n型场效应晶体管的具有第一宽度的间隔物，以及产生具有用于p型场效应晶体管的第二宽度的间隔物，第一宽度大于第二宽度，并且在半导体晶片上沉积硅化物材料，使得在n型场效应的沟道内形成拉伸机械应力在p型场效应晶体管的沟道内形成晶体管和压应力。

9. 发明授权

US07429752B2 Method and structure for forming strained SI for CMOS devices 有权
标题翻译：用于形成CMOS器件的应变SI的方法和结构
公开(公告)号：US07429752B2
公开(公告)日：2008-09-30
申请号：US11534526
申请日：2006-09-22
申请人： An L Steegen , Haining S. Yang , Ying Zhang
发明人： An L Steegen , Haining S. Yang , Ying Zhang
IPC分类号： H01L29/772
CPC分类号： H01L29/7833 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02658 , H01L21/26506 , H01L21/76224 , H01L21/76232 , H01L21/76283 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/1054 , H01L29/665 , H01L29/66575 , H01L29/78 , H01L29/7842 , H01L29/7846 , H01L29/7849
摘要： A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.
摘要翻译：半导体器件包括具有在半导体衬底的一部分下延伸的至少一个间隙的半导体衬底。栅极堆叠在半导体衬底上。应变层形成在至少一个间隙的至少一部分中。应变层仅形成在半导体器件的源极区域和漏极区域中的至少一个之下。

10. 发明授权

US07550338B2 Method and structure for forming strained SI for CMOS devices 失效
标题翻译：用于形成CMOS器件的应变SI的方法和结构
公开(公告)号：US07550338B2
公开(公告)日：2009-06-23
申请号：US11854829
申请日：2007-09-13
申请人： An L. Steegen , Haining S. Yang , Ying Zhang
发明人： An L. Steegen , Haining S. Yang , Ying Zhang
IPC分类号： H01L21/8238
CPC分类号： H01L29/7833 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02658 , H01L21/26506 , H01L21/76224 , H01L21/76232 , H01L21/76283 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/1054 , H01L29/665 , H01L29/66575 , H01L29/78 , H01L29/7842 , H01L29/7846 , H01L29/7849
摘要： A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.
摘要翻译：半导体器件包括具有在半导体衬底的一部分下延伸的至少一个间隙的半导体衬底。栅极堆叠在半导体衬底上。应变层形成在至少一个间隙的至少一部分中。应变层仅形成在半导体器件的源极区域和漏极区域中的至少一个之下。

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