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1. 发明授权

US07326983B2 Selective silicon-on-insulator isolation structure and method 有权
标题翻译：选择性绝缘体上硅绝缘体隔离结构及方法
公开(公告)号：US07326983B2
公开(公告)日：2008-02-05
申请号：US11082993
申请日：2005-03-17
申请人： An L. Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
发明人： An L. Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
IPC分类号： H01L27/108
CPC分类号： H01L29/66651 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0653 , H01L29/66772
摘要： A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.
摘要翻译：本发明的第一方面是一种形成隔离结构的方法，包括：（a）提供半导体衬底; （b）在衬底中形成掩埋的N掺杂区域; （c）在所述衬底中形成垂直沟槽，所述沟槽延伸到所述N掺杂区域中; （d）去除所述N掺杂区域以形成与所述垂直沟槽连通并垂直于所述垂直沟槽延伸的横向沟槽; 和（e）至少部分地填充横向沟槽并用一种或多种绝缘材料填充垂直沟槽。

2. 发明授权

US07923786B2 Selective silicon-on-insulator isolation structure and method 有权
标题翻译：选择性绝缘体上硅绝缘体隔离结构及方法
公开(公告)号：US07923786B2
公开(公告)日：2011-04-12
申请号：US11871249
申请日：2007-10-12
申请人： An L. Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
发明人： An L. Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
IPC分类号： H01L21/70
CPC分类号： H01L29/66651 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0653 , H01L29/66772
摘要： A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.
摘要翻译：本发明的第一方面是一种形成隔离结构的方法，包括：（a）提供半导体衬底; （b）在衬底中形成掩埋的N掺杂区域; （c）在所述衬底中形成垂直沟槽，所述沟槽延伸到所述N掺杂区域中; （d）去除所述N掺杂区域以形成与所述垂直沟槽连通并垂直于所述垂直沟槽延伸的横向沟槽; 和（e）至少部分地填充横向沟槽并用一种或多种绝缘材料填充垂直沟槽。

3. 发明授权

US06936522B2 Selective silicon-on-insulator isolation structure and method 失效
标题翻译：选择性绝缘体上硅绝缘体隔离结构及方法
公开(公告)号：US06936522B2
公开(公告)日：2005-08-30
申请号：US10604102
申请日：2003-06-26
申请人： An L. Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
发明人： An L. Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
IPC分类号： H01L21/336 , H01L21/76 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L21/84 , H01L27/12 , H01L29/76 , H01L31/062
CPC分类号： H01L29/66651 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0653 , H01L29/66772
摘要： A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.
摘要翻译：本发明的第一方面是一种形成隔离结构的方法，包括：（a）提供半导体衬底; （b）在衬底中形成掩埋的N掺杂区域; （c）在所述衬底中形成垂直沟槽，所述沟槽延伸到所述N掺杂区域中; （d）去除所述N掺杂区域以形成与所述垂直沟槽连通并垂直于所述垂直沟槽延伸的横向沟槽; 和（e）至少部分地填充横向沟槽并用一种或多种绝缘材料填充垂直沟槽。

4. 发明申请

US20080029818A1 SELECTIVE SILICON-ON-INSULATOR ISOLATION STRUCTURE AND METHOD 有权
标题翻译：选择性绝缘子绝缘体隔离结构和方法
公开(公告)号：US20080029818A1
公开(公告)日：2008-02-07
申请号：US11871249
申请日：2007-10-12
申请人： An Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
发明人： An Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
IPC分类号： H01L27/12
CPC分类号： H01L29/66651 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0653 , H01L29/66772
摘要： A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.
摘要翻译：本发明的第一方面是一种形成隔离结构的方法，包括：（a）提供半导体衬底; （b）在衬底中形成掩埋的N掺杂区域; （c）在所述衬底中形成垂直沟槽，所述沟槽延伸到所述N掺杂区域中; （d）去除所述N掺杂区域以形成与所述垂直沟槽连通并垂直于所述垂直沟槽延伸的横向沟槽; 和（e）至少部分地填充横向沟槽并用一种或多种绝缘材料填充垂直沟槽。

5. 发明申请

US20050164468A1 Selective silicon-on-insulator isolation structure and method 有权
公开(公告)号：US20050164468A1
公开(公告)日：2005-07-28
申请号：US11082993
申请日：2005-03-17
申请人： An Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
发明人： An Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
IPC分类号： H01L21/336 , H01L21/76 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L21/84 , H01L27/12 , H01L29/76 , H01L31/062
CPC分类号： H01L29/66651 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0653 , H01L29/66772
摘要： A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.

6. 发明申请

US20070143733A1 Method of compensating photomask data for the effects of etch and lithography processes 有权
标题翻译：补偿光掩模数据的方法，用于蚀刻和光刻工艺的影响
公开(公告)号：US20070143733A1
公开(公告)日：2007-06-21
申请号：US11541921
申请日：2006-10-02
申请人： Franz Zach , Jesus Carrero , Bayram Yenikaya , Gokhan Percin , Xuelong Cao , Abdurrahman Sezginer
发明人： Franz Zach , Jesus Carrero , Bayram Yenikaya , Gokhan Percin , Xuelong Cao , Abdurrahman Sezginer
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method for synthesizing a photomask data set from a given target layout, including the following steps: (a) providing a set of target polygons for the target layout; (b) fitting a smooth curve to a target polygon of the set of target polygons, the curve having a set of etch-target points; (c) moving the etch target points according to a model of an etch process to produce a set of lithography-target points; and (d) synthesizing a photomask data set based on a model of a lithography process and the set of lithography-target points.
摘要翻译：一种用于从给定目标布局合成光掩模数据集的方法，包括以下步骤：（a）为目标布局提供一组目标多边形; （b）将平滑曲线拟合到所述目标多边形集合的目标多边形，所述曲线具有一组蚀刻目标点; （c）根据蚀刻工艺的模型移动蚀刻目标点以产生一组光刻目标点; 以及（d）基于光刻工艺的模型和所述一组光刻目标点合成光掩模数据集。

7. 发明申请

US20060266243A1 Calibration on wafer sweet spots 有权
标题翻译：校准晶圆甜点
公开(公告)号：US20060266243A1
公开(公告)日：2006-11-30
申请号：US11139551
申请日：2005-05-31
申请人： Gokhan Percin , Ram Ramanujam , Franz Zach , Abdurrahman Sezginer , Chi-Song Horng , Roy Prasad
发明人： Gokhan Percin , Ram Ramanujam , Franz Zach , Abdurrahman Sezginer , Chi-Song Horng , Roy Prasad
IPC分类号： B41F33/00 , B41F1/54
CPC分类号： G03F7/70441 , G03F1/36 , G03F1/44 , G03F1/68
摘要： A method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips. More particularly, a method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips based on the parameters of test patterns measured at the “wafer sweet spots” so as to arrive at an accurate model.
摘要翻译：提供了一种产生OPC模型的方法，其考虑了在制造半导体芯片的过程中发生的跨晶片变化。更具体地，提供了一种用于生成OPC模型的方法，其考虑了在基于在“晶片甜点”处测量的测试图案的参数的制造半导体芯片的过程期间发生的跨晶片变化，以便到达准确模型。

8. 发明申请

US20070006116A1 Method for real time monitoring and verifying optical proximity correction model and method 有权
标题翻译：用于实时监测和验证光学邻近校正模型和方法的方法
公开(公告)号：US20070006116A1
公开(公告)日：2007-01-04
申请号：US11169616
申请日：2005-06-30
申请人： Gokhan Percin , Ram Ramanujam , Franz Zach , Koichi Suzuki
发明人： Gokhan Percin , Ram Ramanujam , Franz Zach , Koichi Suzuki
IPC分类号： G06F17/50
CPC分类号： G03F1/84 , G03F1/36 , G03F1/44 , G03F7/70441 , G03F7/70683
摘要： This invention relates to a method for real time monitoring and verifying optical proximity correction (OPC) models and methods in production. Prior to OPC is performed on the integrated circuit layout, a model describing the optical, physical and chemical processes involving lithography should be obtained accurately and precisely. In general, the model is calibrated using the measurements obtained by running wafers through the same lithography, patterning, and etch processes. In this invention, a novel real time method for verifying and monitoring the calibrated model on a production or monitor wafer is presented: optical proximity corrected (OPC-ed) test and verification structures are placed on scribe lines or cut lines of the production or monitor wafer, and with pre-determined schedule, the critical dimensions and images of these test and verification structures are monitored across wafer and across exposure field.
摘要翻译：本发明涉及一种用于实时监测和验证生产中的光学邻近校正（OPC）模型和方法的方法。在对集成电路布局进行OPC之前，应准确准确地描述涉及光刻的光学，物理和化学过程的模型。通常，使用通过相同的光刻，图案化和蚀刻工艺运行晶片获得的测量来校准模型。在本发明中，提出了一种用于在生产或监控晶圆上验证和监测校准模型的新型实时方法：将光学邻近校正（OPC-ed）测试和验证结构放置在生产或监视器的划线或切割线上晶圆，并且具有预定的时间表，这些测试和验证结构的关键尺寸和图像在晶片和曝光场之间进行监测。

9. 发明申请

US20060282814A1 Method for verifying and choosing lithography model 有权
公开(公告)号：US20060282814A1
公开(公告)日：2006-12-14
申请号：US11141805
申请日：2005-05-31
申请人： Gokhan Percin , Ram Ramanujam , Franz Zach
发明人： Gokhan Percin , Ram Ramanujam , Franz Zach
IPC分类号： G06F17/50
CPC分类号： G03F7/70616 , G03F7/705 , G03F7/70516
摘要： A test mask with both verification structures and calibration structures is provided to enable the formation of an image of at least one verification structure and at least one calibration structure at a plurality of different test site locations under different dose and defocus conditions to allow the calibration structures to be measured and to obtain at least one computational model for optical proximity correction purposes.

10. 发明申请

US20060268254A1 Method for measuring and verifying stepper illumination 有权
标题翻译：步进照明的测量和验证方法
公开(公告)号：US20060268254A1
公开(公告)日：2006-11-30
申请号：US11141803
申请日：2005-05-31
申请人： Gokhan Percin , Abdurrahman Sezginer , Franz Zach
发明人： Gokhan Percin , Abdurrahman Sezginer , Franz Zach
IPC分类号： G03B27/72
CPC分类号： G03F7/7025 , G03F7/70591
摘要： An apparatus and method for characterizing an illumination pupil of an exposure tool comprises forming a plurality of pinhole test patterns at a plurality of test site locations to facilitate locating test pattern edges for extracting therefrom the illumination pupil characteristics of the exposure tool.
摘要翻译：用于表征曝光工具的照明光瞳的装置和方法包括在多个测试位置处形成多个针孔测试图案，以便于定位测试图案边缘以从其中提取曝光工具的照明光瞳特性。

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