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1. 发明授权

US08063685B1 Pulsed flip-flop circuit 有权
标题翻译：脉冲触发器电路
公开(公告)号：US08063685B1
公开(公告)日：2011-11-22
申请号：US12852514
申请日：2010-08-08
申请人： Kapil Narula , Amol Agarwal , Sumeet Aggarwal , Sunit K. Bansal , Sabaa Sandhu , Harkaran Singh
发明人： Kapil Narula , Amol Agarwal , Sumeet Aggarwal , Sunit K. Bansal , Sabaa Sandhu , Harkaran Singh
IPC分类号： H03K3/00
CPC分类号： H03K3/012 , H03K3/356121
摘要： A flip-flop circuit includes a data input, a clock input for receiving a clock signal having active edges and inactive edges, a data output, an input circuit, a pulse generator, and a latch. The input circuit sets first and second nodes to different initial logic states in response to an inactive edge of the clock signal, and selectively changes the logic state of either the first node or the second node in response to a pulse input signal to control the state of a third node, such that the selection depends on the logic state of the data input. The pulse generator circuit enables the pulse input signal in response to an active edge of the clock signal, and disables the pulse input signal in response to detecting the change in the initial logic state of either the first node or the second node. The latch stores a data output signal for output at the data output, the data output signal depending on the logic state of the third node.
摘要翻译：触发器电路包括数据输入端，用于接收具有有效边沿和无效边沿的时钟信号的时钟输入，数据输出，输入电路，脉冲发生器和锁存器。输入电路响应于时钟信号的不活动边缘将第一和第二节点设置到不同的初始逻辑状态，并且响应于脉冲输入信号选择性地改变第一节点或第二节点的逻辑状态以控制状态第三节点的选择取决于数据输入的逻辑状态。脉冲发生器电路响应于时钟信号的有效沿使能脉冲输入信号，并且响应于检测到第一节点或第二节点的初始逻辑状态的变化而禁用脉冲输入信号。锁存器存储用于在数据输出端输出的数据输出信号，数据输出信号取决于第三节点的逻辑状态。

2. 发明授权

US08291368B2 Method for reducing surface area of pad limited semiconductor die layout 有权
标题翻译：减少焊盘限制半导体管芯布局的表面积的方法
公开(公告)号：US08291368B2
公开(公告)日：2012-10-16
申请号：US13020814
申请日：2011-02-04
申请人： Chetan Verma , Sumeet Aggarwal , Meng Kong Lye
发明人： Chetan Verma , Sumeet Aggarwal , Meng Kong Lye
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/40 , H01L24/06 , H01L2224/05553 , H01L2224/49113
摘要： A method for reducing a surface area of a pad limited semiconductor die layout includes choosing an outer die pad row from a group of outer die pad rows on the semiconductor die, each of the outer die pad rows being adjacent an edge of the semiconductor die. Next, the method performs selecting, from the outer die pad row, a common die pad group with die pads that are arranged to be electrically connected to an external connection pad. The method then performs repositioning a subgroup of the common die pad group on an inner die pad row, the inner pad row being adjacent the outer die pad row. After he repositioning there is performed a step of adjusting positions of at least some of the remaining pads in the outer die pad row thereby reducing an overall length of the outer die pad row. The method then provides for repeating the above steps until the surface area of a pad limited semiconductor die cannot be reduced any further by the step of adjusting positions or until every common die pad group, on every one of the outer die pad rows, has been selected by the selecting step.
摘要翻译：一种用于减小焊盘限制半导体管芯布局的表面积的方法包括从半导体管芯上的一组外管芯焊盘行中选择外管芯焊盘行，每个外管芯焊盘排与半导体管芯的边缘相邻。接下来，该方法执行从外管芯焊盘行中选择配置为电连接到外部连接焊盘的管芯焊盘的公共管芯焊盘组。然后，该方法执行将内部焊盘排上的公共管芯焊盘组的子组重新定位，内部焊盘排与外部管芯焊盘排相邻。在重新定位之后，执行调整外部管芯焊盘列中的至少一些剩余焊盘的位置的步骤，从而减小外部管芯焊盘排的总长度。该方法然后提供重复上述步骤，直到通过调整位置的步骤不再进一步减小衬垫限制半导体管芯的表面积，或者直到在每个外管芯焊盘排上的每个公共管芯焊盘组已被通过选择步骤选择。

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