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1. 发明申请

US20060163635A1 CAPACITOR BELOW THE BURIED OXIDE OF SOI CMOS TECHNOLOGIES FOR PROTECTION AGAINST SOFT ERRORS 失效
标题翻译： SOI CMOS技术的BIOI氧化物电容器防止软错误
公开(公告)号：US20060163635A1
公开(公告)日：2006-07-27
申请号：US10905906
申请日：2005-01-26
申请人： John Aitken , Ethan Cannon , Philip Oldiges , Alvin Strong
发明人： John Aitken , Ethan Cannon , Philip Oldiges , Alvin Strong
IPC分类号： H01L29/76
CPC分类号： H01L27/1203 , H01L29/92
摘要： Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.
摘要翻译：公开了一种包含用于降低结构内的器件的软错误率的电容器的半导体结构。多层半导体结构包括通过有源硅层，第一绝缘体层和第一体层形成并延伸到第二绝缘体层的绝缘体填充的深沟槽隔离结构。所形成的第一体层的隔离部分限定第一电容器板。与第一电容器板相邻的第二绝缘体层的一部分用作电容器电介质。硅衬底或由第三绝缘体层和另一个深沟槽隔离结构隔离的第二体层的一部分可以用作第二电容器板。第一电容器触点直接地或经由线阵列将第一电容器板耦合到器件的电路节点，以便增加电路节点的临界电荷Qcrit。

2. 发明申请

US20070272961A1 CAPACITOR BELOW THE BURIED OXIDE OF SOI CMOS TECHNOLOGIES FOR PROTECTION AGAINST SOFT ERRORS 有权
标题翻译： SOI CMOS技术的BIOI氧化物电容器防止软错误
公开(公告)号：US20070272961A1
公开(公告)日：2007-11-29
申请号：US11838931
申请日：2007-08-15
申请人： John Aitken , Ethan Cannon , Philip Oldiges , Alvin Strong
发明人： John Aitken , Ethan Cannon , Philip Oldiges , Alvin Strong
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L29/92
摘要： Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.
摘要翻译：公开了一种包含用于降低结构内的器件的软错误率的电容器的半导体结构。多层半导体结构包括通过有源硅层，第一绝缘体层和第一体层形成并延伸到第二绝缘体层的绝缘体填充的深沟槽隔离结构。所形成的第一体层的隔离部分限定第一电容器板。与第一电容器板相邻的第二绝缘体层的一部分用作电容器电介质。硅衬底或由第三绝缘体层和另一个深沟槽隔离结构隔离的第二体层的一部分可以用作第二电容器板。第一电容器触点直接地或经由线阵列将第一电容器板耦合到器件的电路节点，以便增加电路节点的临界电荷Qcrit。

3. 发明申请

US20070195841A1 CHARGE NEUTRALIZATION IN SEMICONDUCTOR STRUCTURES 失效
标题翻译：半导体结构中的电荷中和
公开(公告)号：US20070195841A1
公开(公告)日：2007-08-23
申请号：US11276248
申请日：2006-02-21
申请人： John Aitken , Ethan Cannon , Alvin Strong
发明人： John Aitken , Ethan Cannon , Alvin Strong
IPC分类号： H01S5/00
CPC分类号： H01L21/743 , H01L21/76275
摘要： A method for neutralizing trapped charges in a buried oxide layer. The method includes providing a semiconductor structure which includes (a) a semiconductor layer, (b) a charge accumulation layer on top of the semiconductor layer, and (c) a doped region in direct physical contact with the semiconductor layer, wherein the charge accumulation layer comprises trapped charges of a first sign, and wherein the doped region and the semiconductor layer form a P-N junction diode. Next, free charges are generated in the P-N junction diode, wherein the free charges are of a second sign opposite to the first sign. Next, the free charges are accelerated towards the charge accumulation layer, resulting in some of the free charges entering the charge accumulation layer and neutralizing some of the trapped charges in the charge accumulation layer.
摘要翻译：一种用于中和掩埋氧化物层中的俘获电荷的方法。该方法包括提供半导体结构，该半导体结构包括（a）半导体层，（b）半导体层顶部的电荷累积层，和（c）与该半导体层直接物理接触的掺杂区域，其中电荷累积层包括第一符号的俘获电荷，并且其中所述掺杂区域和所述半导体层形成PN结二极管。接下来，在P-N结二极管中产生自由电荷，其中自由电荷是与第一符号相反的第二符号。接下来，免费电荷朝向电荷累积层加速，导致一些自由电荷进入电荷累积层并中和电荷累积层中的一些俘获电荷。

4. 发明申请

US20060103007A1 HEATER FOR ANNEALING TRAPPED CHARGE IN A SEMICONDUCTOR DEVICE 失效
标题翻译：用于在半导体器件中退火捕获电荷的加热器
公开(公告)号：US20060103007A1
公开(公告)日：2006-05-18
申请号：US10904483
申请日：2004-11-12
申请人： John Aitken , Ethan Cannon , Philip Oldiges , Alvin Strong
发明人： John Aitken , Ethan Cannon , Philip Oldiges , Alvin Strong
IPC分类号： H01L21/48 , H01L23/34
CPC分类号： H01L24/80 , H01L23/345 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2924/00
摘要： A structure and associated method for annealing a trapped charge from a semiconductor device. The semiconductor structure comprises a substrate and a first heating element. The substrate comprises a bulk layer, an insulator layer and a device layer. The first heating element is formed within the bulk layer. A first side of the first heating element is adjacent to a first portion of the insulator layer. The first heating element is adapted to be selectively activated to generate thermal energy to heat the first portion of the insulator layer and anneal a trapped electrical charge from the first portion of the insulator layer.
摘要翻译：一种从半导体器件退火俘获电荷的结构和相关方法。半导体结构包括基板和第一加热元件。衬底包括体层，绝缘体层和器件层。第一加热元件形成在本体层内。第一加热元件的第一侧与绝缘体层的第一部分相邻。第一加热元件适于被选择性地激活以产生热能来加热绝缘体层的第一部分并且从绝缘体层的第一部分退火被俘获的电荷。

5. 发明授权

US5046567A Adiabatically induced ignition of combustible materials 失效
标题翻译：绝热诱发可燃材料的点火
公开(公告)号：US5046567A
公开(公告)日：1991-09-10
申请号：US435061
申请日：1989-11-13
申请人： John Aitken , Victorio L. Oria
发明人： John Aitken , Victorio L. Oria
IPC分类号： E21B43/117 , E21B43/1185 , F42D1/04
CPC分类号： E21B43/1185 , E21B43/117 , F42D1/04
摘要： A method and apparatus for achieving adiabatic heat ignition of combustible material, particularly explosive compositions which involves entrapping a quantity of gas in a chamber which is in communication with the combustible material and suddenly compressing the gas to the extent that the temperature thereof is increased adiabatically to the ignition temperature of the combustible material. The apparatus is particularly adaptable for use as an adiabatic ignition device for detonating cord and shaped charges of perforating guns for completion of wells. A quantity of high explosive within an explosive barrel is in detonating proximity with the detonating cord. A cylinder forms an air chamber which is in communication with the explosive composition and is provided with a piston for compression of the gas. One or more shear pins or other locking devices are provided to secure the piston in immovable relation with the cylinder. A force is caused to act on the piston which force is typically induced by fluid pressure within the well which acts on the piston and which may also be induced. As this force reaches a predetermined magnitude, or by means of a weight bar dropped or lowered on wireline from the surface, the piston will be released and the force will drive the piston into the cylinder, compressing the gas sufficiently to raise the temperature of the gas adiabatically to the ignition temperature of the explosive composition.
摘要翻译：一种用于实现可燃材料的绝热热点火的方法和装置，特别是爆炸性组合物，其包括将一定数量的气体夹在与可燃材料连通的室中，并突然压缩气体至其温度绝热地增加可燃材料的点火温度。该装置特别适合用作绝热点火装置，用于引爆穿孔枪的绳索和成形装置以完成井。爆炸桶内的一些高爆炸物与引爆绳引爆。气缸形成与炸药组合物连通的空气室，并设置有用于压缩气体的活塞。提供一个或多个剪切销或其他锁定装置以将活塞固定在与气缸不固定的关系上。使力作用在活塞上，该力通常由作用于活塞的井内的流体压力引起，并且也可能被引起。当该力达到预定的大小时，或者通过重量条从表面下降或下降，活塞将被释放，并且该力将活塞驱动到气缸中，以充分压缩气体以提高温度气体绝热至爆炸组合物的着火温度。

6. 发明授权

US4106902A Ammonia treatment of textile materials 失效
标题翻译：氨处理纺织材料
公开(公告)号：US4106902A
公开(公告)日：1978-08-15
申请号：US628319
申请日：1975-11-03
申请人： John Aitken , William Eric Graham
发明人： John Aitken , William Eric Graham
IPC分类号： D06M11/60 , D06M1/08
CPC分类号： D06M11/60
摘要： A process of treating textile material of a cellulosic nature with ammonia includes the step of first applying water to the textile material before the material is impregnated with ammonia. The amount of water applied must be enough to raise the moisture content of the material to a level above that normally present in the prevailing conditions of atmospheric humidity but with a maximum value of 30% by weight of the dry material.
摘要翻译：用氨处理纤维素性质的纺织材料的方法包括在材料浸渍氨之前首先将水施加到纺织材料上的步骤。施加的水量必须足以将材料的水分含量提高到通常在大气湿度的主要条件下存在的水平，但最大值为干物质的30重量％。

7. 发明授权

US5802836A Method for making thread using substantially equal overfeed to an intermingling device 失效
标题翻译：用于使线程使用基本相等的过量进给到混合装置的方法
公开(公告)号：US5802836A
公开(公告)日：1998-09-08
申请号：US640932
申请日：1996-07-08
申请人： William Wingate Curran , John Aitken
发明人： William Wingate Curran , John Aitken
IPC分类号： D02G1/16 , D02G1/18 , D02G3/46 , D01H13/26
CPC分类号： D02J1/08 , D02G1/162 , D02G1/18 , D02G3/46 , Y10S57/908
摘要： A method of making yarn comprises feeding at least two drawn, continuous filament starting yarns (18, 19), of which at least one is a multifilament yarn, together to an intermingling device (21) to form a single bulked thread of which the filaments of the starting yarns are intermingled and looped, and applying a bulk-reducing treatment to the bulked thread (27), characterized in that the starting yarns are fed to the intermingling device with substantially equal overfeed.
摘要翻译： PCT No.PCT / GB94 / 02455 Sec。 371日期：1996年7月8日 102（e）日期1996年7月8日PCT 1994年11月8日PCT PCT。出版物WO95 / 14124 日期1995年5月26日一种制造纱线的方法包括将至少两根拉伸的连续长丝起始纱线（18,19）馈送到混合装置（21）中，其中至少一根是复丝纱线，以形成单个填充线其中起始纱线的长丝混合和缠绕，并且对膨体螺纹（27）进行体积减少处理，其特征在于，起始纱线以大致相等的过量进给进料到混合装置。

8. 发明授权

US5802683A Method for making unbulked thread 失效
标题翻译：制造未涂抹线的方法
公开(公告)号：US5802683A
公开(公告)日：1998-09-08
申请号：US646342
申请日：1997-04-18
申请人： William Wingate Curran , John Aitken
发明人： William Wingate Curran , John Aitken
IPC分类号： D02G3/46 , D02G1/20 , D02J1/22
CPC分类号： D02G3/46
摘要： A method for making a thread comprising: feeding at least two drawn, continuous filament starting threads (18, 19), of which at least one is a multi-filament thread, together to an intermingling device (21) to form a single bulked thread of which the filaments of the starting threads are intermingled and looped, and applying a bulk-reducing treatment to the bulked thread characterized in that the bulk-reducing treatment comprises a treatment under tension without the thread being heated.
摘要翻译：一种用于制造螺纹的方法，包括：将至少两个拉伸的连续的长丝起始螺纹（18,19）馈送到混合装置（21）中，其中至少一个是多丝线，以形成单个填充螺纹其中起始丝线的长丝混合和缠绕，并且对膨松螺纹施加体积减小处理，其特征在于，本体减少处理包括在没有螺纹被加热的情况下在张力下的处理。

9. 发明申请

US20060267144A1 Trench type buried on-chip precision programmable resistor 有权
公开(公告)号：US20060267144A1
公开(公告)日：2006-11-30
申请号：US11481514
申请日：2006-07-06
申请人： John Aitken , Fen Chen , Timothy Sullivan
发明人： John Aitken , Fen Chen , Timothy Sullivan
IPC分类号： H01L29/00
CPC分类号： H01L28/20 , H01L27/101
摘要： An on-chip, ultra-compact, and programmable semiconductor resistor device and device structure and a method of fabrication. Each semiconductor resistor device structure is formed of one or more conductively connected buried trench type resistor elements exhibiting a precise resistor value. At least two semiconductor resistor device structures may be connected in series or in parallel configuration through the intermediary of one or more fuse devices that may be blown to achieve a desired total resistance value.

10. 发明申请

US20050263850A1 TRENCH TYPE BURIED ON-CHIP PRECISION PROGRAMMABLE RESISTOR 失效
标题翻译： TRENCH型抛光芯片精密可编程电阻器
公开(公告)号：US20050263850A1
公开(公告)日：2005-12-01
申请号：US10709727
申请日：2004-05-25
申请人： John Aitken , Fen Chen , Timothy Sullivan
发明人： John Aitken , Fen Chen , Timothy Sullivan
IPC分类号： H01L21/20 , H01L27/10 , H01L29/00
CPC分类号： H01L28/20 , H01L27/101
摘要： An on-chip, ultra-compact, and programmable semiconductor resistor device and device structure and a method of fabrication. Each semiconductor resistor device structure is formed of one or more conductively connected buried trench type resistor elements exhibiting a precise resistor value. At least two semiconductor resistor device structures may be connected in series or in parallel configuration through the intermediary of one or more fuse devices that may be blown to achieve a desired total resistance value.
摘要翻译：一种片上超小型可编程半导体电阻器件及器件结构及其制造方法。每个半导体电阻器件结构由表现出精确电阻值的一个或多个导电连接的埋沟槽型电阻器元件形成。至少两个半导体电阻器件结构可以通过一个或多个保险丝器件的中间串联或并联配置连接，该熔丝器件可以被吹制以实现期望的总电阻值。

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