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1. 发明授权

US07580477B2 Transmission system enabling reliable reception by a single device of information in channels concurrently transmitted on different frequencies 有权
标题翻译：传输系统能够通过单个设备在不同频率上同时传输的信道中的信息进行可靠的接收
公开(公告)号：US07580477B2
公开(公告)日：2009-08-25
申请号：US10354675
申请日：2003-01-30
申请人： Franck Thebault
发明人： Franck Thebault
IPC分类号： H04L27/00
CPC分类号： H04B7/2656
摘要： This device utilizes frames transported on carriers of different frequencies (BCCH ext CBCH(SD/8)). For processing the information coming from these frames, the device comprises a transceiver circuit (10) including a phase-locked loop for a local oscillator (12). The information is distributed over these frames in locations so that the loop has time to phase lock the local oscillator (12) for receiving information contained in another frame of a different carrier.
摘要翻译：该设备利用在不同频率的载波上传输的帧（BCCH ext CBCH（SD / 8））。为了处理来自这些帧的信息，该设备包括收发器电路（10），其包括用于本地振荡器（12）的锁相环。信息在这些帧上分布在位置上，使得循环有时间锁相本地振荡器（12），用于接收包含在不同载波的另一帧中的信息。

2. 发明申请

US20090201083A1 AMPLIFIER DEVICE AND SYSTEM USING THE DEVICE 审中-公开
标题翻译：放大器装置和使用该装置的系统
公开(公告)号：US20090201083A1
公开(公告)日：2009-08-13
申请号：US12367289
申请日：2009-02-06
申请人： Federico Guanziroli , Germano Nicollini
发明人： Federico Guanziroli , Germano Nicollini
IPC分类号： H03F3/38
CPC分类号： H03F3/217
摘要： A device comprising: an input for an electric signal; an integrator stage connected to said input to provide an integrated signal; an amplifier stage electrically coupled to the integrator stage to receive said integrated signal and to provide an output signal. The device being characterized in that the integrator stage is such that the integrated signal is obtained by an individual signal integration operation.
摘要翻译：一种装置，包括：用于电信号的输入; 连接到所述输入端以提供积分信号的积分器级; 放大器级，电耦合到积分器级以接收所述积分信号并提供输出信号。该装置的特征在于，积分器级使得通过单独的信号积分操作获得积分信号。

3. 发明申请

US20090189643A1 CONSTANT VOLTAGE GENERATING DEVICE 审中-公开
标题翻译：恒电压发电装置
公开(公告)号：US20090189643A1
公开(公告)日：2009-07-30
申请号：US12343012
申请日：2008-12-23
申请人： Dharmaray M. Nedalgi
发明人： Dharmaray M. Nedalgi
IPC分类号： H03K19/20 , H03K19/094 , H03K19/003
CPC分类号： G05F3/24
摘要： A constant voltage generator device provides a first and a second transistor having their main current path coupled serially via a common terminal for providing a constant output voltage at the common terminal of said transistors. The device provides one or more potential dividers having a plurality of serially connected resistive elements. A first voltage is obtained from a first combination of resistive elements of the potential divider and a second voltage obtained from a second combination of resistive elements of the potential divider. The first and the second voltages are supplied to the first and the second voltage at the control terminals of the first and the second transistors, respectively.
摘要翻译：恒压发生器装置提供第一和第二晶体管，其主电流路径经由公共端串联连接，用于在所述晶体管的公共端提供恒定的输出电压。该器件提供具有多个串联连接的电阻元件的一个或多个电位分压器。从分压器的电阻元件的第一组合和从分压器的电阻元件的第二组合获得的第二电压获得第一电压。第一和第二电压分别被提供给第一和第二晶体管的控制端的第一和第二电压。

4. 发明申请

US20090180522A1 FIRST SIGNIFICANT PATH DETECTION 有权
标题翻译：第一重要路径检测
公开(公告)号：US20090180522A1
公开(公告)日：2009-07-16
申请号：US12326762
申请日：2008-12-02
申请人： Stefania Sesia , Giuseppe Montalbano , Pierre Demaj
发明人： Stefania Sesia , Giuseppe Montalbano , Pierre Demaj
IPC分类号： H04B1/707
CPC分类号： H04B1/7115 , H04B1/7117
摘要： A scheme determines the first significant path (FSP) of a received multipath signal, from data defining the relative delay and the amplitude of the individual signal paths occurring in a series of time frames. The scheme includes filtering the data to spread the signal paths, performing a persistence test between frames to reject spurious signal paths, combining the energy of the signal paths in a frame, applying a test to determine the time at which the combined energy satisfies a criterion, and selecting the FSP dependent on that time. The combined energy may be evaluated within a sliding window, and the position of the window within the frame determined that maximizes the combined energy. Alternatively, the combined energy may be evaluated as the cumulative energy through the frame, and the position determined at which the cumulative energy reaches a threshold.
摘要翻译：方案从定义在一系列时间帧中出现的各个信号路径的相对延迟和振幅的数据确定接收的多路径信号的第一有效路径（FSP）。该方案包括对数据进行滤波以扩展信号路径，在帧之间执行持续测试以抑制寄生信号路径，组合帧中的信号路径的能量，应用测试来确定组合能量满足标准的时间，并根据该时间选择FSP。可以在滑动窗口内评估组合的能量，并且确定框架内的窗口的位置使得组合的能量最大化。或者，可以将组合的能量评估为通过该帧的累积能量，以及确定累积能量达到阈值的位置。

5. 发明申请

US20090143095A1 INTER-MODE INTERFERENCE PREVENTION IN A MULTIMODE WIRELESS DEVICE 审中-公开
标题翻译：多模式无线设备中的模式间干扰预防
公开(公告)号：US20090143095A1
公开(公告)日：2009-06-04
申请号：US12270703
申请日：2008-11-13
申请人： Xuejun Zhang
发明人： Xuejun Zhang
IPC分类号： H04M1/00
CPC分类号： H04B1/005 , H04B1/109 , H04B15/00 , H04B2215/068 , H04L1/0001 , H04L27/0006 , H04W24/10 , H04W72/082 , H04W88/06
摘要： This invention relates to a device, a method, a computer program and a computer program product for a device capable of communicating in a first mode of wireless communication and a second mode of wireless communication simultaneously, wherein it is determined for each of at least one channel of a plurality of channels whether interference occurs between the first mode and the second mode; and wherein the channels which have been determined not to cause interference are stored in a list of preferable channels. For instance, in the case where the first mode represents a cellular communications mode, during a cell selection/reselection procedure of the first mode, instead of searching in the cell information stored for the PLMN, it will first search in the list of preferable channels when the second mode is active.
摘要翻译：本发明涉及能够以无线通信的第一模式和第二无线通信模式同时进行通信的装置的装置，方法，计算机程序和计算机程序产品，其中确定每个至少一个在第一模式和第二模式之间发生干扰的多个通道的通道; 并且其中已经被确定为不引起干扰的信道被存储在优选信道的列表中。例如，在第一模式表示蜂窝通信模式的情况下，在第一模式的小区选择/重选过程中，代替在PLMN存储的小区信息中搜索，它将首先在优选信道列表中搜索当第二种模式处于活动状态时。

6. 发明申请

US20090307401A1 CIRCUIT AND METHOD FOR BRIDGING MULTIPLE SOURCE AHB SLAVES TO A TARGET AHB SLAVE 审中-公开
标题翻译：将多个源AHB SLAVES连接到目标AHB SLAVE的电路和方法
公开(公告)号：US20090307401A1
公开(公告)日：2009-12-10
申请号：US12473835
申请日：2009-05-28
申请人： Cunrong Feng
发明人： Cunrong Feng
IPC分类号： G06F13/00
CPC分类号： G06F13/4031
摘要： A circuit and method for bridging multiple source Advanced High-performance Bus (AHB) slaves to a target AHB slave are provided. The circuit uses multiple slave controllers and a multiplexing device to handle signals between the multiple source AHB slaves and the target AHB slave to avoid conflicts between the multiple source AHB slaves to access the target AHB slave.
摘要翻译：提供了一种用于将多个源高级高性能总线（AHB）从站桥接到目标AHB从站的电路和方法。该电路使用多个从属控制器和多路复用装置来处理多个源AHB从站和目标AHB从站之间的信号，以避免多个源AHB从站之间的冲突以访问目标AHB从站。

7. 发明申请

US20090190709A1 PHASE LOCKED LOOP CALIBRATION 有权
标题翻译：相位锁定校准
公开(公告)号：US20090190709A1
公开(公告)日：2009-07-30
申请号：US12357918
申请日：2009-01-22
申请人： Herve Marie
发明人： Herve Marie
IPC分类号： H03D3/24
CPC分类号： H03C3/0925 , H03C3/0941 , H03C3/095
摘要： A method for controlling a modulation signal for modulating a phase locked loop. A scaling control signal for scaling the modulation signal is generated using the error signal of the phase locked loop. The scaling control signal is adjusted when the modulation signal and the phase of the modulation signal have the same sign.
摘要翻译：一种用于控制用于调制锁相环的调制信号的方法。使用锁相环的误差信号产生用于缩放调制信号的缩放控制信号。当调制信号和调制信号的相位具有相同符号时，调节缩放控制信号。

8. 发明授权

US07558361B2 Phase-switching dual modulus prescaler 有权
标题翻译：相位切换双模预分频器
公开(公告)号：US07558361B2
公开(公告)日：2009-07-07
申请号：US10573733
申请日：2004-09-28
申请人： Dominicus Martinus Wilhelmus Leenaerts , Nenad Pavlovic , Ketan Mistry
发明人： Dominicus Martinus Wilhelmus Leenaerts , Nenad Pavlovic , Ketan Mistry
IPC分类号： H03K21/00
CPC分类号： H03K23/667 , H03K23/662 , H03L7/193
摘要： A phase-switching dual modulus prescaler having a dual modulus divider is provided. Said divider comprises a first and second divide-by-2 circuit (A;B), wherein said second divide-by-2 circuit (B) is coupled to the output of said first divide-by-2 circuit (A) and at least said second divide-by-two circuit (B) comprises a four phase output each separated by 90°. A phase selection unit (PSU) is provided for selecting one of the four phase outputs (Ip, In, Qp, Qn; INi, INni, INq, Innq) of the second divide-by-2 circuit (B). Moreover, a phase control unit is provided for providing control signal (C1, NC0; C2, NC2; C3, NC3) to the phase selection unit, wherein the phase selection unit (PSU) performs the selection of the four phase outputs (Ip, In, Qp, Qn; INi, INni, INq, Innq) according to the control signals (C0, NC0; C1, NC1; C2, NC2). Said phase selection unit (PSU) is implemented based on direct logic. The implementation of the phase selection unit based on direct logic enables a higher speed and saves area on the chip.
摘要翻译：提供了具有双模数分频器的相位切换双模预分频器。所述分频器包括第一和第二除以2电路（A; B），其中所述第二分频电路（B）耦合到所述第一分频电路（A）的输出端，并且在至少所述第二分频电路（B）包括每相分开90°的四相输出。提供相位选择单元（PSU），用于选择第二分频电路（B）的四个相位输出（Ip，In，Qp，Qn; INi，INni，INq，Innq）之一。此外，提供一个相位控制单元，用于向相位选择单元提供控制信号（C1，NC0; C2，NC2; C3，NC3），其中相位选择单元（PSU）执行四相输出（Ip，根据控制信号（C0，NC0; C1，NC1; C2，NC2），输入，Qp，Qn，INi，INni，INq，Innq）。所述相位选择单元（PSU）是基于直接逻辑实现的。基于直接逻辑的相位选择单元的实现能够实现更高的速度并节省芯片上的面积。

9. 发明授权

US07480846B2 Iterative turbo decoder with single memory 有权
标题翻译：具有单个存储器的迭代turbo解码器
公开(公告)号：US07480846B2
公开(公告)日：2009-01-20
申请号：US10514288
申请日：2003-05-07
申请人： Sébastien Charpentier , Patrick Valdenaire
发明人： Sébastien Charpentier , Patrick Valdenaire
IPC分类号： H04L13/00 , G06F5/00
CPC分类号： H03M13/2984 , H03M13/2782 , H03M13/2957 , H03M13/6563
摘要： The invention relates to the domain of turbo decoders. Such a decoder comprises a first decoder (14) and a second decoder (16), each decoder being able to calculate extrinsic output data from extrinsic input data coming from the other decoder. The decoding circuit according to the invention comprises a single memory (31) for storing the extrinsic data. When a decoder calculates an extrinsic output data from an extrinsic input data coming from the other decoder and stored in the single memory at a certain address, this extrinsic output data is then written at this same address.
摘要翻译：本发明涉及涡轮解码器的领域。这样的解码器包括第一解码器（14）和第二解码器（16），每个解码器能够从来自另一解码器的外部输入数据计算外部输出数据。根据本发明的解码电路包括用于存储外在数据的单个存储器（31）。当解码器从来自另一个解码器的外部输入数据计算外部输出数据并存储在特定地址的单个存储器中时，该外部输出数据然后被写入该相同的地址。

10. 发明申请

US20100121897A1 Filter Block for Compensating Droop in a Frequency Response of a Signal 有权
标题翻译：用于补偿信号频率响应中的下降的滤波器块
公开(公告)号：US20100121897A1
公开(公告)日：2010-05-13
申请号：US12614004
申请日：2009-11-06
申请人： Ankur Bal , Anupam Jain
发明人： Ankur Bal , Anupam Jain
IPC分类号： G06F17/17
CPC分类号： H03H17/0286 , H03H17/0671
摘要： The invention may provide a method and filter block for compensating droop in a frequency response of a signal. The filter block may include a decimator, which decimates a high frequency input signal to a set frequency output signal. The set frequency can be, for example, the Nyquist frequency for the input signal. Further, the filter block may include a droop compensator that compensates the droop in the frequency response of the output signal from the decimator. The droop compensator may be made using recursive filters, as opposed to large tap FIR filters, which may result in less memory consumption and decreased power consumption.
摘要翻译：本发明可以提供一种用于在信号的频率响应中补偿下降的方法和滤波器块。滤波器块可以包括抽取器，其将高频输入信号抽取到设定频率输出信号。设定频率可以是例如输入信号的奈奎斯特频率。此外，滤波器块可以包括下降补偿器，其补偿来自抽取器的输出信号的频率响应中的下降。下降补偿器可以使用递归滤波器制造，而不是大抽头FIR滤波器，这可能导致较少的存储器消耗和降低的功耗。

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