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1. 发明授权

US5677687A Zero DC power keyboard scanner using bidirectional I/O's with repeaters 失效
标题翻译：零直流电源键盘扫描仪，使用带中继器的双向I / O
公开(公告)号：US5677687A
公开(公告)日：1997-10-14
申请号：US676557
申请日：1996-07-08
申请人： Patrick Valdenaire
发明人： Patrick Valdenaire
IPC分类号： H03M11/20 , H03K17/94 , H03M11/00
CPC分类号： H03M11/20
摘要： The present invention is directed to a system and methodology where virtually no DC power dissipation is used during keyboard scanning or key closure. This is done by replacing the passive pull-up (or pull down) resistors of previous schemes by input/output (I/O) circuits with repeaters and utilizing a scanning protocol and methodology which take advantage of the bidirectional I/O devices with repeaters. In a preferred embodiment, a plurality of CMOS bidirectional I/O circuits with repeaters are used, one for each row and column line in a switch matrix. A low power, switch activation scanner circuit determines activation of a switch. The circuit is coupled to or may include a plurality of switches, arranged in rows and columns, each row output line intersecting each column output line at a different node, for coupling a first row to a first column at a first node when a first switch of the plurality of switches is activated. A plurality of bidirectional input/output devices is arranged as two sets arranged in a matrix fashion. A first set of the two sets is comprised of a plurality of rows and a second set of the two sets comprising a plurality of columns. Each input/output device is comprised of an input to the input/output device, an output coupled to an output line, an output control for controlling the output of the input/output device such that a predetermined control signal coupled to the output control enables a signal coupled to the input to pass through to the output or places the output in a high impedance state, and a repeater circuit, coupled to the output of the input/output device, for holding the most current signal level at the output when the I/O device output is in a high impedance state.
摘要翻译：本发明涉及一种系统和方法，其中在键盘扫描或键关闭期间实际上不使用DC功率消耗。这是通过使用具有中继器的输入/输出（I / O）电路替换先前方案的无源上拉（或下拉）电阻，并利用利用具有中继器的双向I / O设备的扫描协议和方法。在优选实施例中，使用具有中继器的多个CMOS双向I / O电路，一个用于开关矩阵中的每行和列线。低功率开关激活扫描器电路确定开关的启动。电路耦合到或可以包括以行和列布置的多个开关，每个行输出线在不同节点处与每个列输出线交叉，用于当第一开关在第一节点处将第一行耦合到第一列时的多个开关被激活。多个双向输入/输出装置被布置为以矩阵方式排列的两组。两组的第一组由多个行组成，第二组两组包括多个列。每个输入/输出设备包括输入到输入/输出设备的输入，耦合到输出线的输出，用于控制输入/输出设备的输出的输出控制，使得耦合到输出控制的预定控制信号实现耦合到输入端的信号传递到输出或将输出置于高阻抗状态;以及中继器电路，耦合到输入/输出设备的输出，用于在输出端保持最新的信号电平 I / O设备输出处于高阻态。

2. 发明授权

US5059978A Resistor-string digital to analog converters with auxiliary coarse ladders 失效
标题翻译：带辅助粗梯的电阻串数模转换器
公开(公告)号：US5059978A
公开(公告)日：1991-10-22
申请号：US631602
申请日：1990-12-20
申请人： Patrick Valdenaire
发明人： Patrick Valdenaire
IPC分类号： H03M1/06 , H03M1/68 , H03M1/76
CPC分类号： H03M1/0678 , H03M1/685 , H03M1/765
摘要： A digital to analog converter for the conversion of a digital signal into a corresponding analog signal. The converter has a resistive string comprising a string of first resistive segments having between segments selectable nodes including intermediate nodes wherein consecutive intermediate nodes are separated by a respective plurality of said segments. Switches provide selective coupling of at least one of the selectable nodes to an output. A decoder is responsive to the digital signal for controlling the switches. In order to reduce the output impedance of the converter and to reduce variation in the output impedance with the position of the selected node at least one auxiliary string of second resistive segments is coupled in parallel with the resistive string, providing between intermediate nodes substantially lower impedance than the respective first segments.
摘要翻译：用于将数字信号转换成相应模拟信号的数模转换器。该转换器具有电阻串，其包括一串第一电阻段，其具有在包括中间节点之间的可选节点之间，其中连续的中间节点由相应的多个所述段分隔开。开关提供至少一个可选节点与输出的选择性耦合。解码器响应数字信号来控制开关。为了减小转换器的输出阻抗并且通过所选择的节点的位置来减小输出阻抗的变化，至少一个第二电阻段的辅助串与电阻串并联耦合，在中间节点之间提供基本上更低的阻抗比相应的第一段。

3. 发明授权

US07480846B2 Iterative turbo decoder with single memory 有权
标题翻译：具有单个存储器的迭代turbo解码器
公开(公告)号：US07480846B2
公开(公告)日：2009-01-20
申请号：US10514288
申请日：2003-05-07
申请人： Sébastien Charpentier , Patrick Valdenaire
发明人： Sébastien Charpentier , Patrick Valdenaire
IPC分类号： H04L13/00 , G06F5/00
CPC分类号： H03M13/2984 , H03M13/2782 , H03M13/2957 , H03M13/6563
摘要： The invention relates to the domain of turbo decoders. Such a decoder comprises a first decoder (14) and a second decoder (16), each decoder being able to calculate extrinsic output data from extrinsic input data coming from the other decoder. The decoding circuit according to the invention comprises a single memory (31) for storing the extrinsic data. When a decoder calculates an extrinsic output data from an extrinsic input data coming from the other decoder and stored in the single memory at a certain address, this extrinsic output data is then written at this same address.
摘要翻译：本发明涉及涡轮解码器的领域。这样的解码器包括第一解码器（14）和第二解码器（16），每个解码器能够从来自另一解码器的外部输入数据计算外部输出数据。根据本发明的解码电路包括用于存储外在数据的单个存储器（31）。当解码器从来自另一个解码器的外部输入数据计算外部输出数据并存储在特定地址的单个存储器中时，该外部输出数据然后被写入该相同的地址。

4. 发明申请

US20050180513A1 Memory for turbo decoder 有权
标题翻译：内存为turbo解码器
公开(公告)号：US20050180513A1
公开(公告)日：2005-08-18
申请号：US10514288
申请日：2003-05-07
申请人： Sebastien Charpentier , Patrick Valdenaire
发明人： Sebastien Charpentier , Patrick Valdenaire
IPC分类号： H03M13/27 , H03M13/29 , H04L1/00 , H04B14/06
CPC分类号： H03M13/2984 , H03M13/2782 , H03M13/2957 , H03M13/6563
摘要： The invention relates to the domain of turbo decoders. Such a decoder comprises a first decoder (14) and a second decoder (16), each decoder being able to calculate extrinsic output data from extrinsic input data coming from the other decoder. The decoding circuit according to the invention comprises a single memory (31) for storing the extrinsic data When a decoder calculates an extrinsic output data from an extrinsic input data coming from the other decoder and stored in the single memory at a certain address, this extrinsic output data is then written at this same address.
摘要翻译：本发明涉及涡轮解码器的领域。这样的解码器包括第一解码器（14）和第二解码器（16），每个解码器能够从来自另一解码器的外部输入数据计算外部输出数据。根据本发明的解码电路包括用于存储外部数据的单个存储器（31）。当解码器从来自另一个解码器的外部输入数据计算外部输出数据并存储在单个存储器中的特定地址时，该外部然后将输出数据写入同一地址。

5. 发明授权

US5455582A Digital to analog converter employing R-2R ladders with substituted shunt arms 失效
标题翻译：采用具有取代分流臂的R-2R梯形的数模转换器
公开(公告)号：US5455582A
公开(公告)日：1995-10-03
申请号：US992338
申请日：1992-12-17
申请人： Patrick Valdenaire
发明人： Patrick Valdenaire
IPC分类号： H03M1/78
CPC分类号： H03M1/785
摘要： A digital-to-analog converter of the R/2R ladder type is composed of two individually asymmetric ladders symmetrically coupled to a differential amplifier. Switch means in the shunt arms of the ladders are controlled so that the same number of shunt arms are connected to each of a pair of input or output nodes irrespective of the value of the controlling digital signal. The most significant shunt arm in each ladder may be configured as an equivalent of that part of the respective ladder extending from the respective stage node towards the least significant end of the ladder.
摘要翻译： R / 2R梯形类型的数/模转换器由对称耦合到差分放大器的两个单独的不对称梯子组成。控制梯形的分流臂中的开关装置被控制，使得相同数量的分流臂连接到一对输入或输出节点中的每一个，而与控制数字信号的值无关。每个梯子中最重要的分流臂可以被配置为等同于从各个舞台节点向梯子的最低有效端延伸的相应梯子的那部分。

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