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1. 发明授权

US07480846B2 Iterative turbo decoder with single memory 有权
标题翻译：具有单个存储器的迭代turbo解码器
公开(公告)号：US07480846B2
公开(公告)日：2009-01-20
申请号：US10514288
申请日：2003-05-07
申请人： Sébastien Charpentier , Patrick Valdenaire
发明人： Sébastien Charpentier , Patrick Valdenaire
IPC分类号： H04L13/00 , G06F5/00
CPC分类号： H03M13/2984 , H03M13/2782 , H03M13/2957 , H03M13/6563
摘要： The invention relates to the domain of turbo decoders. Such a decoder comprises a first decoder (14) and a second decoder (16), each decoder being able to calculate extrinsic output data from extrinsic input data coming from the other decoder. The decoding circuit according to the invention comprises a single memory (31) for storing the extrinsic data. When a decoder calculates an extrinsic output data from an extrinsic input data coming from the other decoder and stored in the single memory at a certain address, this extrinsic output data is then written at this same address.
摘要翻译：本发明涉及涡轮解码器的领域。这样的解码器包括第一解码器（14）和第二解码器（16），每个解码器能够从来自另一解码器的外部输入数据计算外部输出数据。根据本发明的解码电路包括用于存储外在数据的单个存储器（31）。当解码器从来自另一个解码器的外部输入数据计算外部输出数据并存储在特定地址的单个存储器中时，该外部输出数据然后被写入该相同的地址。

2. 发明授权

US06993699B2 Turbo decoding apparatus and interleave-deinterleave apparatus 失效
标题翻译： Turbo解码装置和交错解交织装置
公开(公告)号：US06993699B2
公开(公告)日：2006-01-31
申请号：US10352515
申请日：2003-01-28
申请人： Kazuhisa Obuchi , Tetsuya Yano , Kazuo Kawabata , Takaharu Nakamura
发明人： Kazuhisa Obuchi , Tetsuya Yano , Kazuo Kawabata , Takaharu Nakamura
IPC分类号： H03M13/27 , H03M13/29
CPC分类号： H03M13/2984 , H03M13/2707 , H03M13/275 , H03M13/2764 , H03M13/2767 , H03M13/2771 , H03M13/2782 , H03M13/2785 , H03M13/6505 , H04L1/005 , H04L1/0066 , H04L1/0071
摘要： In an apparatus such as a turbo decoding apparatus in which it is necessary to carry out interleave operation and deinterleave operation, there are provided a memory unit (5) and a memory control unit (12) capable of changing data writing order and data reading order with respect to the memory unit (5) depending on whether data is to be interleaved or deinterleaved. With this arrangement, the single unit of memory (5) can function as an interleaver and a deinterleaver, thereby reducing the size and cost the device.
摘要翻译：在需要执行交错操作和解交织操作的Turbo解码装置等装置中，设置有能够改变数据写入顺序和数据读取顺序的存储器单元（5）和存储器控制单元（12）相对于存储器单元（5），取决于数据是交织还是解交织。通过这种布置，单个存储器单元（5）可以用作交织器和解交织器，从而减小设备的尺寸和成本。

3. 发明授权

US06662331B1 Space-efficient turbo decoder 有权
标题翻译：节省空间的turbo解码器
公开(公告)号：US06662331B1
公开(公告)日：2003-12-09
申请号：US09699252
申请日：2000-10-27
申请人： Inyup Kang
发明人： Inyup Kang
IPC分类号： H03M1300
CPC分类号： H03M13/3905 , H03M13/2975 , H03M13/2984 , H03M13/6502 , H03M13/6505 , H03M13/6563
摘要： An efficient turbo decoder. The disclosed turbo decoder includes a first mode of operation in which the turbo decoder uses a first functional loop. The first functional loop includes a memory bank, a read interleaver, a first multiplexer (MUX), a RAM file, a log-MAP decoder, a write interleaver, and a second MUX. The disclosed turbo decoder further includes a second mode of operation in which a second functional loop is used. The second functional loop includes the memory bank, the first MUX, the RAM file, the log-MAP decoder, and the second MUX. The memory bank is a dual port extrinsic memory. The disclosed turbo decoder circuit switches between the first mode and the second mode.
摘要翻译：一种高效的turbo解码器。所公开的turbo解码器包括第一操作模式，其中turbo解码器使用第一功能回路。第一功能循环包括存储体，读交织器，第一多路复用器（MUX），RAM文件，对数MAP解码器，写交织器和第二MUX。所公开的turbo解码器还包括使用第二功能回路的第二操作模式。第二功能循环包括存储体，第一MUX，RAM文件，log-MAP解码器和第二MUX。存储器是双端口外部存储器。所公开的turbo解码器电路在第一模式和第二模式之间切换。

4. 发明授权

US07533306B2 Turbo decoding apparatus and interleave-deinterleave apparatus 有权
标题翻译： Turbo解码装置和交错解交织装置
公开(公告)号：US07533306B2
公开(公告)日：2009-05-12
申请号：US11296678
申请日：2005-12-07
申请人： Kazuhisa Obuchi , Tetsuya Yano , Kazuo Kawabata , Takaharu Nakamura
发明人： Kazuhisa Obuchi , Tetsuya Yano , Kazuo Kawabata , Takaharu Nakamura
IPC分类号： H03M13/27
CPC分类号： H03M13/2984 , H03M13/2707 , H03M13/275 , H03M13/2764 , H03M13/2767 , H03M13/2771 , H03M13/2782 , H03M13/2785 , H03M13/6505 , H04L1/005 , H04L1/0066 , H04L1/0071
摘要： In an apparatus such as a turbo decoding apparatus in which it is necessary to carry out interleave operation and deinterleave operation, there are provided a memory unit (5) and a memory control unit (12) capable of changing data writing order and data reading order with respect to the memory unit (5) depending on whether data is to be interleaved or deinterleaved. With this arrangement, the single unit of memory (5) can function as an interleaver and a deinterleaver, thereby reducing the size and cost the device.
摘要翻译：在需要执行交错操作和解交织操作的Turbo解码装置等装置中，设置有能够改变数据写入顺序和数据读取顺序的存储器单元（5）和存储器控制单元（12）相对于存储器单元（5），取决于数据是交织还是解交织。通过这种布置，单个存储器单元（5）可以用作交织器和解交织器，从而减小设备的尺寸和成本。

5. 发明授权

US06732327B1 Scaled-feedback turbo decoder 失效
标题翻译：缩放反馈turbo解码器
公开(公告)号：US06732327B1
公开(公告)日：2004-05-04
申请号：US09565502
申请日：2000-05-05
申请人： Marko Heinila
发明人： Marko Heinila
IPC分类号： H03M1303
CPC分类号： H03M13/2957 , H03M13/2984 , H03M13/3905 , H03M13/658
摘要： An iterative Turbo decoder in which soft bits of a received signal are repetitively subjected to the process of decoding by a first decoder associated with a first encoder in the transmitter, interleaving by an interleaver associated with an interleaver in the transmitter, decoding by a second decoder associated with a second encoder in the transmitter, and deinterleaving by a deinterleaver associated with the interleaver in the transmitter. The improvement is to scale the signal after each decoding by a predetermined value in the vicinity of 0.7 to 0.8. At a signal Eb/No in the vicinity of 1.0 db., an improvement of about 0.2 db. in coding gain is attained while very little complexity is added. Decoders may be according to the max Log MAP algorithm instead of the more complex Log MAP algorithm with only slight degradation of performance.
摘要翻译：一种迭代Turbo解码器，其中接收信号的软比特重复地经由与发射机中的第一编码器相关联的第一解码器的解码处理，由与发射机中的交织器相关联的交织器进行交织，由第二解码器进行解码与发射机中的第二编码器相关联，以及由发射机中与交织器相关联的去交织器进行解交织。改进之处在于在每个解码之后将信号缩小0.7到0.8附近的预定值。在1.0db附近的信号Eb / No处，改善约0.2db。在增加编码增益的同时，增加了很少的复杂度。解码器可以根据最大的Log MAP算法代替更复杂的Log MAP算法，其性能只有轻微的降低。

6. 发明授权

US06625778B1 Turbo error-correcting decoder and turbo error-correcting decoding method 失效
标题翻译： Turbo纠错解码器和turbo纠错解码方法
公开(公告)号：US06625778B1
公开(公告)日：2003-09-23
申请号：US09654067
申请日：2000-09-01
申请人： Takahiko Nakamura , Hachiro Fujita , Hideo Yoshida
发明人： Takahiko Nakamura , Hachiro Fujita , Hideo Yoshida
IPC分类号： H03M1300
CPC分类号： H03M13/658 , H03M13/2957 , H03M13/2984
摘要： In a conventional turbo error-correcting decoder, the soft-decision information is corrected by using an average value (A) and a variance value (&sgr;2) of reliability of received bits. From the reliability-corrected soft-decision information, the hard-decision information is obtained. This process of calculation is complex, giving rise to a problem of reduced processing speed and complicated circuit. To deal with this problem, an average value of reliability of received information bits is determined and then a ratio between the average value and the soft-decision information is also determined. This ratio is converted by the conversion table into the reliability-corrected soft-decision information, from which the hard-decision information is obtained.
摘要翻译：在传统的turbo纠错解码器中，通过使用接收比特的可靠性的平均值（A）和方差值（sigma <2>）来校正软判决信息。从可靠性校正的软判决信息中，获得硬决策信息。这个计算过程很复杂，导致处理速度降低和电路复杂的问题。为了解决这个问题，确定接收信息比特的可靠性的平均值，然后确定平均值和软判决信息之间的比率。该比率由转换表转换为可靠性校正的软判决信息，从中获得硬决策信息。

7. 发明授权

US06574766B2 Turbo decoding apparatus and interleave-deinterleave apparatus 有权
公开(公告)号：US06574766B2
公开(公告)日：2003-06-03
申请号：US09823564
申请日：2001-03-30
申请人： Kazuhisa Obuchi , Tetsuya Yano , Kazuo Kawabata , Takaharu Nakamura
发明人： Kazuhisa Obuchi , Tetsuya Yano , Kazuo Kawabata , Takaharu Nakamura
IPC分类号： H03M1329
CPC分类号： H03M13/2984 , H03M13/2707 , H03M13/275 , H03M13/2764 , H03M13/2767 , H03M13/2771 , H03M13/2782 , H03M13/2785 , H03M13/6505 , H04L1/005 , H04L1/0066 , H04L1/0071
摘要： In an apparatus such as a turbo decoding apparatus in which it is necessary to carry out interleave operation and deinterleave operation, there are provided a memory unit (5) and a memory control unit (12) capable of changing data writing order and data reading order with respect to the memory unit (5) depending on whether data is to be interleaved or deinterleaved. With this arrangement, the single unit of memory (5) can function as an interleaver and a deinterleaver, thereby reducing the size and cost the device.

8. 发明申请

US20010014962A1 Turbo decoding apparatus and interleave-deinterleave apparatus 有权
标题翻译： Turbo解码装置和交错解交织装置
公开(公告)号：US20010014962A1
公开(公告)日：2001-08-16
申请号：US09823564
申请日：2001-03-30
发明人： Kazuhisa Obuchi , Tetsuya Yano , Kazuo Kawabata , Takaharu Nakamura
IPC分类号： H03M013/03
CPC分类号： H03M13/2984 , H03M13/2707 , H03M13/275 , H03M13/2764 , H03M13/2767 , H03M13/2771 , H03M13/2782 , H03M13/2785 , H03M13/6505 , H04L1/005 , H04L1/0066 , H04L1/0071
摘要： In an apparatus such as a turbo decoding apparatus in which it is necessary to carry out interleave operation and deinterleave operation, there are provided a memory unit (5) anda memory control unit (12) capable ofchanging data writing order and data reading order with respect to the memory unit (5) depending on whether data is to be interleaved or deinterleaved. With this arrangement, the single unit of memory (5) can function as an interleaver and a deinterleaver, thereby reducing the size and cost the device.
摘要翻译：在需要执行交织操作和解交织操作的Turbo解码装置等装置中，设置有存储单元（5）和能够改变数据写入顺序和数据读取顺序的存储器控制单元（12）取决于数据是被交织还是去交织，到存储单元（5）。通过这种布置，单个存储器单元（5）可以用作交织器和解交织器，从而减小设备的尺寸和成本。

9. 发明授权

US11799500B2 PMD-to-TC-MAC interface with 2-stage FEC protection 有权
公开(公告)号：US11799500B2
公开(公告)日：2023-10-24
申请号：US17810830
申请日：2022-07-05
申请人： MAXLINEAR, INC.
发明人： Gert Schedelbeck , Rainer Strobel , Vladimir Oksman
IPC分类号： H03M13/29 , H03M13/37 , H03M13/00 , H03M13/01 , H03M13/11
CPC分类号： H03M13/2978 , H03M13/2984 , H03M13/3707 , H03M13/6511 , H03M13/015 , H03M13/1108 , H03M13/1117
摘要： A system for a fiber-optic network includes a transceiver. The transceiver includes a fiber-optic interface unit and a host unit. The host unit includes a low-complexity error correction decoder and a high-complexity error correction decoder. One or both from the low-complexity error correction decoder and the high-complexity error correction decoder are selected to decode input data from the fiber-optic interface unit, the input data including codewords.

10. 发明申请

US20120066566A1 ACCESSING MEMORY DURING PARALLEL TURBO DECODING 失效
标题翻译：并行涡轮解码期间的访问记忆
公开(公告)号：US20120066566A1
公开(公告)日：2012-03-15
申请号：US12878934
申请日：2010-09-09
申请人： Zhiqiang Cui , Iwen Yao , Qiang Huang
发明人： Zhiqiang Cui , Iwen Yao , Qiang Huang
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/2984 , H03M13/2707 , H03M13/2775 , H03M13/3905 , H03M13/3972 , H03M13/6566
摘要： A method for accessing extrinsic information in a turbo decoder is disclosed. Operation phases for Forward State Metric Calculators (FSMCs) and Reverse State Metric Calculators (RSMCs) in multiple maximum a posteriori probability (MAP) decoders are misaligned differently based on whether a current half iteration is even or odd. First extrinsic information is read from a memory into the FSMCs and RSMCs using the misaligned operation phases. Second extrinsic information is determined using the MAP decoders. Each row of the second extrinsic information is stored to a different bank in the memory using the misaligned operation phases.
摘要翻译：公开了一种在turbo解码器中访问外部信息的方法。基于当前半迭代是偶数还是奇数，多个最大后验概率（MAP）解码器中的前向状态度量计算器（FSMC）和反向状态度量计算器（RSMC）的操作阶段不对齐。使用不对齐的操作阶段，将第一外部信息从存储器读入FSMC和RSMC。使用MAP解码器确定第二外在信息。使用未对准的操作阶段将第二外在信息的每一行存储在存储器中的不同存储体中。

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