会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Medium access for de-centralized wireless network
    • 中型无线网络的中等接入
    • US08605596B2
    • 2013-12-10
    • US11721808
    • 2004-12-20
    • Hong Cheng Michael Sim
    • Hong Cheng Michael Sim
    • H04W4/00
    • H04W84/20H04W48/08
    • A method of wireless medium access for establishing a decentralized wireless network, the method comprising broadcasting of beacon frames by each of a plurality of devices; listening, at each device, for beacon frames of other devices; identifying, at each device, other devices who's beacon frames have been heard; and forming the decentralised wireless network as at least two dynamic networks, each dynamic network being centered around one of the devices and having said other devices who's beacon frames have been heard by said one device as network members.
    • 一种用于建立分散无线网络的无线介质访问方法,所述方法包括通过多个设备中的每一个来广播信标帧; 在每个设备处收听其他设备的信标帧; 在每个设备处识别已经听到信标帧的其他设备; 以及将所述分散无线网络形成为至少两个动态网络,每个动态网络以所述设备之一为中心,并且所述其他设备的信标帧已被所述一个设备作为网络成员听到。
    • 4. 发明申请
    • Systems and methods for multipass servowriting with a null burst pattern
    • 具有零脉冲串模式的多通道伺服驱动的系统和方法
    • US20060215306A1
    • 2006-09-28
    • US11090608
    • 2005-03-25
    • Richard EhrlichDavid Rutherford
    • Richard EhrlichDavid Rutherford
    • G11B21/02G11B5/596
    • G11B5/59655
    • Embodiments of the present invention enables the trimming and writing of servo bursts in a null burst servo pattern as multiple portions in multiple passes while still demodulating each of the servo bursts as a single burst to obtain PES. Alternatively, the servo bursts can be trimmed and written using different currents in different passes respectively so that a gap can be created in the radial direction between the servo bursts. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures, and the claims.
    • 本发明的实施例能够将零脉冲串伺服模式中的伺服脉冲串的修整和写入作为多遍的多个部分,同时将每个伺服脉冲串解调为单个脉冲串以获得PES。 或者,可以分别使用不同电流中的不同电流来修剪和写入伺服脉冲串,使得可以在伺服脉冲串之间的径向上产生间隙。 本说明书不是对本发明的完整描述或限制本发明的范围。 本发明的其它特征,方面和目的可以通过对说明书,附图和权利要求的评述来获得。
    • 6. 发明申请
    • Systems and methods for using worf to identify burst patterns for repair
    • 使用worf识别突发模式进行修复的系统和方法
    • US20050157416A1
    • 2005-07-21
    • US11082120
    • 2005-03-16
    • Richard EhrlichThorsten Schmidt
    • Richard EhrlichThorsten Schmidt
    • G11B5/596G11B21/02G11B27/36
    • G11B5/59633
    • The misplacement of a servo burst during a servowriting or self-servowriting process can be corrected by erasing and re-writing that burst. In addition, WORF information of a track can be saved in memory for future servowriting and/or can be utilized to compare with a pre-determined threshold to identify servo bursts to be repaired. Alternatively, a batch writing approach can be used to minimize the time needed to re-write misplaced bursts. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures, and the claims.
    • 在伺服驱动或自伺服驱动过程中伺服脉冲串的错位可以通过擦除和重新写入该脉冲来校正。 另外,轨道的WORF信息可以保存在存储器中用于将来的伺服驱动和/或可用于与预定阈值进行比较以识别要修复的伺服脉冲串。 或者,可以使用批量写入方法来最小化重新写入错放脉冲串所需的时间。 本说明书不是对本发明的完整描述或限制本发明的范围。 本发明的其它特征,方面和目的可以通过对说明书,附图和权利要求的评述来获得。
    • 9. 发明授权
    • AV Amplifier
    • AV放大器
    • US6167140A
    • 2000-12-26
    • US36689
    • 1998-03-09
    • Atsuo Watanabe
    • Atsuo Watanabe
    • H04R5/04H04S3/00H02B1/00H04R5/00
    • H03F3/68H03F2200/03H03F2200/321H04R5/04H04R2420/03H04S3/00
    • When a first bi-wiring speaker is connected to output terminals 5A and 5B and a second bi-wiring speaker is connected to output terminals 5D and 5E, and further a two-channel stereo reproduction is performed, a signal 3L for a L channel outputted from a decoder 2 is amplified by amplifiers 4A and 4B in parallel to be given to the first bi-wiring speaker in a bi-wiring connecting manner and a signal 3R for a R channel outputted from the decoder 2 is amplified by amplifiers 4C and 4D in parallel and given to the second bi-wiring speaker in a bi-wiring connecting manner. At this time, a gain corrector 7 equalizes a gain which an output signal of the amplifier 4A has with respect to the signal 3L for the L channel with a gain which an output signal of the amplifier 4B has with respect to the signal 3L for the L channel. Similarly, a gain corrector 8 equalizes a gain which an output signal of the amplifier 4C has with respect to the signal 3R for the R channel with a gain which an output signal of the amplifier 4D has with respect to the signal 3R for the R channel.
    • 当第一双线扬声器连接到输出端子5A和5B,并且第二双线扬声器连接到输出端子5D和5E,并且进一步进行双声道立体声再现时,输出用于L声道的信号3L 解码器2由放大器4A和4B并联放大,以双线连接方式被提供给第一双线扬声器,并且从解码器2输出的用于R通道的信号3R被放大器4C和4D放大 并联并以双线连接方式给予第二双线扬声器。 此时,增益校正器7使放大器4A的输出信号相对于L通道的信号3L的增益与放大器4B的输出信号相对于信号3L的增益相等, L通道。 类似地,增益校正器8使放大器4C的输出信号相对于R沟道的信号3R的增益与放大器4D的输出信号相对于R沟道的信号3R具有的增益相等 。
    • 10. 发明授权
    • Data processor
    • 数据处理器
    • US06125438A
    • 2000-09-26
    • US63009
    • 1998-04-21
    • Tadashi OkamotoHiroshi KadotaYoshiteru Mino
    • Tadashi OkamotoHiroshi KadotaYoshiteru Mino
    • G06F15/78G06F15/00
    • G06F15/7857G06F15/7864
    • A data processor of the invention includes plural memories, plural arithmetic units, a data transfer unit and a network. The data transfer unit transfers various data to predetermined memories, and switches the connections between the memories and the arithmetic units by using the network. The control unit adds a processability judgement signal to a data read from a predetermined memory in reading the data, so as to make a pair of the data and the processability judgement signal. Each of the arithmetic units receives the data and the processability judgement signal, conducts predetermined processing on the received data, delays the received processability judgement signal by the number of cycles equal to its own processing cycle, and outputs resultant data obtained through the processing and the delayed processability judgement signal. Accordingly, in storing ultimate resultant data in a predetermined storage unit, the storage unit stores the ultimate resultant data as effective data on the basis of the processability judgement signal added to the resultant data. The data processor attains wide application and can be applied to various types of multimedia applications by switching the connections between the memories and the arithmetic units by using the network.
    • 本发明的数据处理器包括多个存储器,多个运算单元,数据传送单元和网络。 数据传送单元将各种数据传送到预定存储器,并且通过使用网络来切换存储器和算术单元之间的连接。 控制单元在读取数据时,对从预定存储器读取的数据添加可处理性判断信号,以便形成一对数据和加工性判定信号。 每个算术单元接收数据和可处理性判断信号,对接收到的数据进行预定的处理,将接收到的加工性判断信号延迟等于其自身的处理周期的周期数,并输出通过处理获得的结果数据和 延迟加工性判断信号。 因此,在将最终结果数据存储在预定存储单元中时,存储单元基于加到结果数据的加工性判断信号将最终结果数据存储为有效数据。 数据处理器具有广泛的应用,可以通过使用网络切换存储器和算术单元之间的连接来应用于各种类型的多媒体应用。