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1. 发明授权

US07426311B1 Object-based coding and decoding apparatuses and methods for image signals 失效
标题翻译：用于图像信号的基于对象的编码和解码装置和方法
公开(公告)号：US07426311B1
公开(公告)日：2008-09-16
申请号：US09195897
申请日：1998-11-19
申请人： Sung Moon Chun , Jin Hak Lee , Joo Hee Moon , Gwang Hoon Park , Jae Kyoon Kim , Jae-won Chung
发明人： Sung Moon Chun , Jin Hak Lee , Joo Hee Moon , Gwang Hoon Park , Jae Kyoon Kim , Jae-won Chung
IPC分类号： G06K9/36
CPC分类号： H04N19/543 , H04N19/115 , H04N19/12 , H04N19/129 , H04N19/132 , H04N19/14 , H04N19/17 , H04N19/18 , H04N19/21 , H04N19/61
摘要： An object-based coding apparatus and method for image signals, wherein upon scanning shape-adaptive transform coefficients of an input image signal transformed in accordance with a shape-adaptive transform, only segments containing such shape-adaptive transform coefficients are scanned. In the scanning operation, segments containing no transform coefficient are skipped, thereby reducing the quantity of data being encoded. An apparatus for and a method of object-based decoding of image signals are also disclosed which can decode bit streams generated using the coding method, thereby reproducing image signals.
摘要翻译：一种用于图像信号的基于对象的编码装置和方法，其中在扫描根据形状自适应变换变换的输入图像信号的形状自适应变换系数时，仅扫描包含这种形状自适应变换系数的段。在扫描操作中，跳过不包含变换系数的段，从而减少被编码的数据量。还公开了一种用于图像信号的基于对象的解码的装置和方法，其可以解码使用编码方法生成的比特流，从而再现图像信号。

2. 发明申请

US20080217514A1 Pixel for CMOS Image Sensor Having a Select Shape for Low Pixel Crosstalk 审中-公开
标题翻译：具有低像素串扰选择形状的CMOS图像传感器的像素
公开(公告)号：US20080217514A1
公开(公告)日：2008-09-11
申请号：US12104266
申请日：2008-04-16
申请人： Do-Young Lee
发明人： Do-Young Lee
IPC分类号： H01L27/00
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14627 , H01L27/14645 , H04N5/335
摘要： A novel CMOS image unit pixel layout having a photodiode including an optically optimized square image sensing region. The square image sensing layout provides for reduced electrical and color crosstalk and improved modulation transfer function (MTF) between neighboring pixels of an array of pixels.
摘要翻译：一种具有光电二极管的新颖CMOS图像单元像素布局，其包括光学优化的方形图像感测区域方形图像感测布局提供减少的电和色彩串扰以及像素阵列的相邻像素之间的改进的调制传递函数（MTF）。

3. 发明授权

US07122401B2 Area array type semiconductor package fabrication method 失效
标题翻译：面阵阵式半导体封装制造方法
公开(公告)号：US07122401B2
公开(公告)日：2006-10-17
申请号：US09970876
申请日：2001-10-05
申请人： Chi-Jung Song
发明人： Chi-Jung Song
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L23/495 , H01L23/48
CPC分类号： H01L24/81 , H01L23/3107 , H01L23/49503 , H01L24/45 , H01L24/48 , H01L24/97 , H01L2224/16 , H01L2224/16225 , H01L2224/32013 , H01L2224/32225 , H01L2224/32245 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2224/81801 , H01L2224/97 , H01L2924/00014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/83 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： An area array type semiconductor package includes a plurality of conductive media such as solder bumps or solder balls, attached to respective bond pads of a chip. The conductive media act as external output terminals. The chip is attached to a lead frame by a thermal conductive adhesive, and a predetermined area of the lead frame and the semiconductor chip are packaged with a molding resin. Leads of the lead frame are then trimmed and formed so that the lead frame, to which the semiconductor chip is adhered, acts as a heat sink. This allows the package to be used for a high-powered semiconductor device which radiates a high temperature heat. Also, because conductive media such as solder bumps or solder balls can be used to directly connect bond pads of the chip to conductive regions of a circuit board, a size of the semiconductor package can be minimized, the arrangement of the bonding pads on the chip can be easily planned, and electrical characteristics of the semiconductor package can be improved.
摘要翻译：区域阵列型半导体封装包括多个导电介质，例如焊料凸块或焊球，附着到芯片的各个焊盘。导电介质充当外部输出端子。芯片通过导热粘合剂附接到引线框架，引线框架和半导体芯片的预定区域用模制树脂封装。然后对引线框架的引线进行修整和形成，使得半导体芯片粘附到其上的引线框架用作散热器。这允许封装用于辐射高温热的高功率半导体器件。此外，由于可以使用诸如焊料凸块或焊球的导电介质将芯片的接合焊盘直接连接到电路板的导电区域，所以半导体封装的尺寸可以最小化，芯片上的焊盘的布置可以容易地计划，并且可以提高半导体封装的电特性。

4. 发明授权

US07095087B2 Semiconductor device and fabrication method thereof 有权
公开(公告)号：US07095087B2
公开(公告)日：2006-08-22
申请号：US10868216
申请日：2004-06-16
申请人： Chang Soo Lee
发明人： Chang Soo Lee
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/408 , H01L21/761 , H01L21/762 , H01L21/823878 , H01L21/823892 , H01L27/0266 , H01L27/092 , H01L27/0921 , H01L27/10897
摘要： A semiconductor device and fabrication method thereof restrains an amplified current between input voltage Vin and ground voltage Vss, and first and second n-wells are biased into internal voltage sources, whereby the current-voltage characteristic of the input pad becomes stabilized during an open/short checkup of a semiconductor device. The semiconductor device includes a semiconductor substrate having a plurality of device isolation regions, first and second n-wells horizontally spaced from either of the plurality of device isolation regions, a p-channel transistor formed in the second n-well, an input protection transistor horizontally spaced from the first n-well and the device isolation region, on a symmetrical portion by the first n-well to the second n-well, and a guard ring formed between the first n-well and the input protection transistor.

5. 发明授权

US07088772B2 Method and apparatus for updating motion vector memories 有权
标题翻译：用于更新运动矢量存储器的方法和装置
公开(公告)号：US07088772B2
公开(公告)日：2006-08-08
申请号：US09789231
申请日：2001-02-20
申请人： Kyeong Joong Kim , Hyun Soo Kang , Jae Won Chung
发明人： Kyeong Joong Kim , Hyun Soo Kang , Jae Won Chung
IPC分类号： H04N7/12 , H04N11/02
CPC分类号： H04N19/433 , H04N19/51 , H04N19/56
摘要： A method and apparatus for updating motion vector memories used for prediction of motion vectors in a video compression coding/decoding method and system. For a frame composed of N macroblocks in the horizontal direction, only (2N+1) motion vector memories are used to store all motion vectors necessary to motion prediction, and only three memories per macroblock are used to update motion vectors, thereby reducing the size of a circuitry, the amount of computation and the amount of power consumed.
摘要翻译：一种用于更新用于在视频压缩编码/解码方法和系统中预测运动矢量的运动矢量存储器的方法和装置。对于在水平方向上由N个宏块组成的帧，仅使用（2N + 1）个运动矢量存储器来存储运动预测所需的所有运动矢量，并且每个宏块仅使用三个存储器来更新运动矢量，从而减小尺寸的电路，计算量和消耗的功率量。

6. 发明授权

US07071068B2 Transistor and method for fabricating the same 失效
标题翻译：晶体管及其制造方法
公开(公告)号：US07071068B2
公开(公告)日：2006-07-04
申请号：US10889067
申请日：2004-07-13
申请人： Jae Goan Jeong
发明人： Jae Goan Jeong
IPC分类号： H01L21/336
CPC分类号： H01L29/4925 , H01L21/28114 , H01L21/28123
摘要： A transistor and a method for fabricating the same that involves a forming a device isolation oxide film semiconductor substrate, forming an opening in the device isolation oxide to open the substrate and define an active region, the junction between the oxide and the substrate having a rounded profile, and then forming a complex gate electrode structure in the active region. The preferred gate electrode structure comprises a gate oxide and a stacked conductor structure having a first and a second conductor, an optional hard mask layer formed on the second conductor, an oxide layer formed on the first conductor, and nitride spacers formed on the oxide layer on the sidewalls of the gate electrode. On either side of the gate electrode structure lightly doped drain (LDD) regions and source drain regions are then formed in the active region of the semiconductor substrate. The wafer is then planarized with one or more insulating films to condition the wafer for subsequent processing.
摘要翻译：一种晶体管及其制造方法，其包括形成器件隔离氧化膜半导体衬底，在器件隔离氧化物中形成开口以打开衬底并限定有源区，氧化物和衬底之间的接合处具有圆形然后在有源区中形成复杂的栅电极结构。优选的栅电极结构包括栅极氧化物和具有第一和第二导体的叠层导体结构，在第二导体上形成的任选的硬掩模层，形成在第一导体上的氧化物层，以及形成在氧化物层上的氮化物间隔物在栅电极的侧壁上。在栅电极结构的任一侧，然后在半导体衬底的有源区中形成轻掺杂漏极（LDD）区和源漏区。然后将晶片用一个或多个绝缘膜平坦化以调节晶片以用于后续处理。

7. 发明授权

US07026704B2 Semiconductor device for reducing plasma charging damage 有权
标题翻译：用于减少等离子体充电损坏的半导体器件
公开(公告)号：US07026704B2
公开(公告)日：2006-04-11
申请号：US10865845
申请日：2004-06-14
申请人： Ha Zoong Kim
发明人： Ha Zoong Kim
IPC分类号： H01L33/58 , H01L29/00
CPC分类号： H01L21/04 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and method of manufacturing the semiconductor device including a semiconductor substrate of a first conductivity type. A scribe lane area formed in the substrate to define chip formation areas. A deep well area formed in each chip formation area. The deep well area has a second conductivity type which is opposite the first conductivity type. Also, at least one well area is formed within the deep well area.
摘要翻译：一种半导体器件及其制造方法，该半导体器件包括第一导电类型的半导体衬底。在衬底中形成的划线通道区域，以限定芯片形成区域。在每个芯片形成区域形成的深井区域。深井区具有与第一导电类型相反的第二导电类型。此外，在深井区域内形成至少一个井区。

8. 发明申请

US20060028892A1 Ferroelectric memory device and method of making the same 审中-公开
公开(公告)号：US20060028892A1
公开(公告)日：2006-02-09
申请号：US11201213
申请日：2005-08-11
申请人： Hee Kang
发明人： Hee Kang
IPC分类号： G11C7/00
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/105 , H01L27/11507 , H01L27/11517 , H01L28/55
摘要： A ferroelectric memory device, e.g., nonvolatile, has an effective layout by eliminating a separate cell plate line. The ferroelectric memory device includes first and second split word lines formed over first and second active regions of a semiconductor substrate, and the first and second active regions are isolated from each other. Source and drain regions are formed in the first active region on both sides of the first split word line and the second active region on both sides of the second split word line. A conductive barrier layer, a first capacitor electrode and a ferroelectric layer are sequentially formed on the first and second split word lines. Two second capacitor electrodes with one connected to one of the source and drain regions of the second active region is formed over the first split word line. The other one is connected to one of the source and drain regions of the first active region and is formed over the second split word line. First and second bit lines are respectively connected to the other one of the source and drain regions of the first active region, and the other one of the source and drain regions of the second active region.

9. 发明授权

US06937653B2 Rate control apparatus and method for real-time video communication 有权
标题翻译：用于实时视频通信的速率控制装置和方法
公开(公告)号：US06937653B2
公开(公告)日：2005-08-30
申请号：US09861359
申请日：2001-05-18
申请人： Joon-Ho Song , Hyun-Soo Kang , Jae-Won Chung
发明人： Joon-Ho Song , Hyun-Soo Kang , Jae-Won Chung
IPC分类号： H04N19/00 , G06F15/16 , H04N19/126 , H04N19/132 , H04N19/146 , H04N19/176 , H04N19/196 , H04N19/423 , H04N19/70 , H04N19/91 , H04N7/18
CPC分类号： H04N19/587 , H04N19/115 , H04N19/124 , H04N19/132 , H04N19/149 , H04N19/152 , H04N19/164 , H04N19/172 , H04N19/176 , H04N19/196 , H04N19/197 , H04N19/61
摘要： A rate control apparatus for real-time video communication includes: an initialization unit for setting an initial value required for rate control according to a transmission speed and the number of input frames; a target bit calculation unit for obtaining the target number of encoding bits, maximum allowable number of bits, and minimum allowable number of bits in consideration of a buffer state and a transmission speed; a rate control and encoder unit for executing rate control and encoding using the maximum allowable number of bits and the minimum allowable number of bits; a stuffing control unit for comparing the size of a bit stream from the rate control and encoding unit with the target number of encoding bits from the target bit calculation unit for thereby outputting stuffing bits; a buffering unit for storing a combination of the bit stream from the rate control encoding unit and the stuffing bits from the stuffing control unit for thereby outputting them to the target bit calculation unit; a frame skip unit for outputting a frame skip signal according to the buffer occupied state signal from the buffering unit; and a control logic unit for controlling an encoding process of each of the above elements and determining whether or not the next input frame is encoded according to the frame skip signal from the frame skip unit.
摘要翻译：一种用于实时视频通信的速率控制装置包括：初始化单元，用于根据传输速度和输入帧数量设置速率控制所需的初始值; 考虑到缓冲状态和传输速度的目标比特计算单元，用于获得目标编码比特数，最大允许比特数和最小允许比特数; 速率控制和编码器单元，用于使用最大允许位数和最小允许位数执行速率控制和编码; 填充控制单元，用于将来自速率控制和编码单元的比特流的大小与来自目标比特计算单元的目标编号比特数进行比较，从而输出填充比特; 缓冲单元，用于存储来自速率控制编码单元的比特流和来自填充控制单元的填充比特的组合，从而将它们输出到目标比特计算单元; 帧跳过单元，用于根据来自缓冲单元的缓冲器占用状态信号输出帧跳过信号; 以及控制逻辑单元，用于控制上述每个元素的编码处理，并根据来自帧跳过单元的帧跳过信号确定下一个输入帧是否被编码。

10. 发明授权

US06936880B2 Capacitor of semiconductor memory device and method of manufacturing the same 失效
标题翻译：半导体存储器件的电容器及其制造方法
公开(公告)号：US06936880B2
公开(公告)日：2005-08-30
申请号：US10323516
申请日：2002-12-18
申请人： Jong Bum Park
发明人： Jong Bum Park
IPC分类号： H01L27/108 , H01L21/02 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/55 , H01L28/90
摘要： A capacitor and a method of manufacturing the same are disclosed. The BST dielectric film is disposed between the lower electrode by coating a sidewall of the upper electrode and then forming the lower electrode in a second contact hole defined by the upper electrode and BST film. As such, degradation in the step coverage characteristic caused by forming a BST dielectric film having a desired composition ratio is avoided.
摘要翻译：公开了一种电容器及其制造方法。 BST电介质膜通过涂覆上电极的侧壁，然后在由上电极和BST膜限定的第二接触孔中形成下电极而设置在下电极之间。因此，避免了通过形成具有所需组成比的BST电介质膜引起的台阶覆盖特性的劣化。

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