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1. 发明授权

US06773976B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06773976B2
公开(公告)日：2004-08-10
申请号：US09820217
申请日：2001-03-29
申请人： Ha Zoong Kim
发明人： Ha Zoong Kim
IPC分类号： H01L218238
CPC分类号： H01L21/04 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and method of manufacturing the semiconductor device including a semiconductor substrate of a first conductivity type. A scribe lane area formed in the substrate to define chip formation areas. A deep well area formed in each chip formation area. The deep well area has a second conductivity type which is opposite the first conductivity type. Also, at least one well area is formed within the deep well area.
摘要翻译：一种半导体器件及其制造方法，该半导体器件包括第一导电类型的半导体衬底。在衬底中形成的划线通道区域，以限定芯片形成区域。在每个芯片形成区域形成的深井区域。深井区具有与第一导电类型相反的第二导电类型。此外，在深井区域内形成至少一个井区。

2. 发明授权

US06351135B1 TDDB test pattern and method for testing TDDB of MOS capacitor dielectric 有权
标题翻译： TDDB测试方法和测试方法，用于测量MOS电容电介质的TDDB
公开(公告)号：US06351135B1
公开(公告)日：2002-02-26
申请号：US09342514
申请日：1999-06-29
申请人： Ha Zoong Kim
发明人： Ha Zoong Kim
IPC分类号： G01R3126
CPC分类号： G01R31/129 , G01R31/1227 , G01R31/2623 , G01R31/2639
摘要： TDDB test pattern which can reduce a test time period and improve a precision of a measurement result statistically; and a method for testing TDDBs of MOS capacitor dielectric films using the same, the TDDB test pattern including a plurality of unit test pattern cells each having an MOS capacitor, an MOS transistor, and a fuse for controlling operations of the MOS capacitor and the MOS transistor, a first voltage supplying unit for supplying a stress voltage to the MOS capacitor and the MOS transistor in each unit test pattern cell on the same time, an ammeter for continuous measurement of a total current from the plurality of unit test pattern cells, to measure a total time to breakdown of the plurality of unit test pattern cells, a plurality of VFN's (Voltage Forcing Nodes) each positioned between the first voltage supplying unit and the fuse in the unit test pattern cell, a DCMN (Drain Current Measuring Node) positioned between the ammeter and a drain terminal of the MOS transistor in each of the plurality of unit test pattern cells, and a second voltage supplying unit for applying a voltage to the drain terminal of the MOS transistor.
摘要翻译： TDDB测试模式，可以减少测试时间，提高测量结果的精度统计; 以及使用其的MOS电容电介质膜的TDDB的测试方法，TDDB测试图案包括多个单元测试图形单元，每个单元测试图形单元均具有MOS电容器，MOS晶体管和用于控制MOS电容器和MOS的操作的熔丝晶体管，用于同时向每个单元测试图形单元中的MOS电容器和MOS晶体管提供应力电压的第一电压提供单元，用于连续测量来自多个单元测试图形单元的总电流的电流表，测量多个单元测试图形单元的总体时间，每个位于单元测试图形单元中的第一电压提供单元和熔丝之间的多个VFN（电压强制节点），DCMN（漏极电流测量节点）位于所述多个单位测试图形单元中的每一个中的所述电流表和所述MOS晶体管的漏极端子之间，以及用于向所述多个单元测试图案单元施加电压的第二电压供应单元的漏极端子。

3. 发明授权

US07479797B2 TDDB test pattern and method for testing TDDB of MOS capacitor dielectric 有权
公开(公告)号：US07479797B2
公开(公告)日：2009-01-20
申请号：US11643656
申请日：2006-12-22
申请人： Ha Zoong Kim
发明人： Ha Zoong Kim
IPC分类号： G01R31/28 , G01R31/14
CPC分类号： G01R31/129 , G01R31/1227 , G01R31/2623 , G01R31/2639
摘要： A Time Dependent Dielectric Breakdown (TDDB) test pattern circuit, which can reduce testing time and statistically improve a precision of measurement as well as a method for testing the test pattern circuit are discussed. Typically, a test pattern circuit includes in plurality of unit test patterns. Each unit test pattern includes a capacitor connected to a stress voltage. The stress voltage is applied to the capacitor and the current flowing from the capacitor is measured over time. The dielectric in the capacitor breaks down over time and at a certain point, the current from the capacitor changes suddenly. Unfortunately, the convention test pattern circuit requires serial testing of each unit cell, and therefore, the measuring time is significant when there are many unit cells involved. The circuit allows for the measurements to take place simultaneously for all unit cells within the test pattern circuit. This greatly reduces the testing time, allows for greater amount of data to be obtained which improves the statistically accuracy, and reduces costs as well.

4. 发明授权

US07170309B2 TDDB test pattern and method for testing TDDB of MOS capacitor dielectric 有权
标题翻译： TDDB测试方法和测试方法，用于测量MOS电容电介质的TDDB
公开(公告)号：US07170309B2
公开(公告)日：2007-01-30
申请号：US10895285
申请日：2004-07-21
申请人： Ha Zoong Kim
发明人： Ha Zoong Kim
IPC分类号： G01R31/28 , G01R31/12
CPC分类号： G01R31/129 , G01R31/1227 , G01R31/2623 , G01R31/2639
摘要： A Time Dependent Dielectric Breakdown (TDDB) test pattern circuit, which can reduce testing time and statistically improve a precision of measurement as well as a method for testing the test pattern circuit are discussed. Typically, a test pattern circuit includes in plurality of unit test patterns. Each unit test pattern includes a capacitor connected to a stress voltage. The stress voltage is applied to the capacitor and the current flowing from the capacitor is measured over time. The dielectric in the capacitor breaks down over time and at a certain point, the current from the capacitor changes suddenly. Unfortunately, the convention test pattern circuit requires serial testing of each unit cell, and therefore, the measuring time is significant when there are many unit cells involved. The circuit allows for the measurements to take place simultaneously for all unit cells within the test pattern circuit. This greatly reduces the testing time, allows for greater amount of data to be obtained which improves the statistically accuracy, and reduces costs as well.
摘要翻译：讨论了一种可以减少测试时间和统计上提高测量精度的时间依赖介质击穿（TDDB）测试图案电路，以及测试图案电路测试方法。通常，测试图案电路包括多个单元测试图案。每个单元测试图案包括连接到应力电压的电容器。应力电压被施加到电容器，并且随着时间的推移测量从电容器流出的电流。电容器中的电介质随时间而分解，在某一点，电容器电流突然变化。不幸的是，会议测试模式电路需要对每个单元进行串行测试，因此当涉及许多单位单元时，测量时间是显着的。电路允许对测试图形电路中的所有单位单元同时进行测量。这大大降低了测试时间，允许获得更大量的数据，从而提高了统计学准确性，并降低了成本。

5. 发明授权

US07026704B2 Semiconductor device for reducing plasma charging damage 有权
标题翻译：用于减少等离子体充电损坏的半导体器件
公开(公告)号：US07026704B2
公开(公告)日：2006-04-11
申请号：US10865845
申请日：2004-06-14
申请人： Ha Zoong Kim
发明人： Ha Zoong Kim
IPC分类号： H01L33/58 , H01L29/00
CPC分类号： H01L21/04 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and method of manufacturing the semiconductor device including a semiconductor substrate of a first conductivity type. A scribe lane area formed in the substrate to define chip formation areas. A deep well area formed in each chip formation area. The deep well area has a second conductivity type which is opposite the first conductivity type. Also, at least one well area is formed within the deep well area.
摘要翻译：一种半导体器件及其制造方法，该半导体器件包括第一导电类型的半导体衬底。在衬底中形成的划线通道区域，以限定芯片形成区域。在每个芯片形成区域形成的深井区域。深井区具有与第一导电类型相反的第二导电类型。此外，在深井区域内形成至少一个井区。

6. 发明授权

US06781401B2 TDDB test pattern and method for testing TDDB of MOS capacitor dielectric 有权
公开(公告)号：US06781401B2
公开(公告)日：2004-08-24
申请号：US09995680
申请日：2001-11-29
申请人： Ha Zoong Kim
发明人： Ha Zoong Kim
IPC分类号： G01R3126
CPC分类号： G01R31/129 , G01R31/1227 , G01R31/2623 , G01R31/2639
摘要： A Time Dependent Dielectric Breakdown (TDDB) test pattern circuit, which can reduce testing time and statistically improve a precision of measurement as well as a method for testing the test pattern circuit are discussed. Typically, a test pattern circuit includes in plurality of unit test patterns. Each unit test pattern includes a capacitor connected to a stress voltage. The stress voltage is applied to the capacitor and the current flowing from the capacitor is measured over time. The dielectric in the capacitor breaks down over time and at a certain point, the current from the capacitor changes suddenly. Unfortunately, the convention test pattern circuit requires serial testing of each unit cell, and therefore, the measuring time is significant when there are many unit cells involved. The circuit allows for the measurements to take place simultaneously for all unit cells within the test pattern circuit. This greatly reduces the testing time, allows for greater amount of data to be obtained which improves the statistically accuracy, and reduces costs as well.

7. 发明授权

US06617229B2 Method for manufacturing transistor of double spacer structure 失效
公开(公告)号：US06617229B2
公开(公告)日：2003-09-09
申请号：US10103692
申请日：2002-03-25
申请人： Ha Zoong Kim
发明人： Ha Zoong Kim
IPC分类号： H01L23205
CPC分类号： H01L29/66492 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method for manufacturing a transistor of a double spacer structure is disclosed, in which a local LDD region is formed by forming a transistor including a gate electrode, and an oxide film spacer and a nitride film spacer formed sequentially, dry etching the oxide film spacer using the nitride film spacer as a mask, and injecting an impurity ion into an LDD region of a portion where the oxide film spacer is etched, short channel effect is prevented and current characteristic of the transistor is improved by combination of the ion injection process considering trade-off relation between the short channel effect and the current characteristic of the transistor during design of a device.

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