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1. 发明授权

US06937653B2 Rate control apparatus and method for real-time video communication 有权
标题翻译：用于实时视频通信的速率控制装置和方法
公开(公告)号：US06937653B2
公开(公告)日：2005-08-30
申请号：US09861359
申请日：2001-05-18
申请人： Joon-Ho Song , Hyun-Soo Kang , Jae-Won Chung
发明人： Joon-Ho Song , Hyun-Soo Kang , Jae-Won Chung
IPC分类号： H04N19/00 , G06F15/16 , H04N19/126 , H04N19/132 , H04N19/146 , H04N19/176 , H04N19/196 , H04N19/423 , H04N19/70 , H04N19/91 , H04N7/18
CPC分类号： H04N19/587 , H04N19/115 , H04N19/124 , H04N19/132 , H04N19/149 , H04N19/152 , H04N19/164 , H04N19/172 , H04N19/176 , H04N19/196 , H04N19/197 , H04N19/61
摘要： A rate control apparatus for real-time video communication includes: an initialization unit for setting an initial value required for rate control according to a transmission speed and the number of input frames; a target bit calculation unit for obtaining the target number of encoding bits, maximum allowable number of bits, and minimum allowable number of bits in consideration of a buffer state and a transmission speed; a rate control and encoder unit for executing rate control and encoding using the maximum allowable number of bits and the minimum allowable number of bits; a stuffing control unit for comparing the size of a bit stream from the rate control and encoding unit with the target number of encoding bits from the target bit calculation unit for thereby outputting stuffing bits; a buffering unit for storing a combination of the bit stream from the rate control encoding unit and the stuffing bits from the stuffing control unit for thereby outputting them to the target bit calculation unit; a frame skip unit for outputting a frame skip signal according to the buffer occupied state signal from the buffering unit; and a control logic unit for controlling an encoding process of each of the above elements and determining whether or not the next input frame is encoded according to the frame skip signal from the frame skip unit.
摘要翻译：一种用于实时视频通信的速率控制装置包括：初始化单元，用于根据传输速度和输入帧数量设置速率控制所需的初始值; 考虑到缓冲状态和传输速度的目标比特计算单元，用于获得目标编码比特数，最大允许比特数和最小允许比特数; 速率控制和编码器单元，用于使用最大允许位数和最小允许位数执行速率控制和编码; 填充控制单元，用于将来自速率控制和编码单元的比特流的大小与来自目标比特计算单元的目标编号比特数进行比较，从而输出填充比特; 缓冲单元，用于存储来自速率控制编码单元的比特流和来自填充控制单元的填充比特的组合，从而将它们输出到目标比特计算单元; 帧跳过单元，用于根据来自缓冲单元的缓冲器占用状态信号输出帧跳过信号; 以及控制逻辑单元，用于控制上述每个元素的编码处理，并根据来自帧跳过单元的帧跳过信号确定下一个输入帧是否被编码。

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