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1. 发明授权

US09679892B2 Method of manufacturing a reverse blocking semiconductor device 有权
公开(公告)号：US09679892B2
公开(公告)日：2017-06-13
申请号：US14986166
申请日：2015-12-31
申请人： Infineon Technologies AG
发明人： Johannes Georg Laven , Roman Baburske , Christian Jaeger , Hans-Joachim Schulze
IPC分类号： H01L29/739 , H01L27/06 , H01L21/04 , H01L29/66 , H01L29/06 , H01L29/08
CPC分类号： H01L27/0664 , H01L21/04 , H01L29/0634 , H01L29/0834 , H01L29/66143 , H01L29/6634 , H01L29/66348 , H01L29/7393 , H01L29/7397
摘要： A reverse blocking semiconductor device is manufactured by introducing impurities of a first conductivity type into a semiconductor substrate of the first conductivity type through a process surface to obtain a process layer extending into the semiconductor substrate up to a first depth, and introducing impurities of a second, complementary conductivity type into the semiconductor substrate through openings of an impurity mask provided on the process surface to obtain emitter zones of the second conductivity type extending up to a second depth deeper than the first depth and channels of the first conductivity type between the emitter zones. Exposed portions of the process layer are removed above the emitter zones.

2. 发明授权

US08941089B2 Resistive switching devices and methods of formation thereof 有权
标题翻译：电阻式开关装置及其形成方法
公开(公告)号：US08941089B2
公开(公告)日：2015-01-27
申请号：US13767800
申请日：2013-02-14
申请人： Adesto Technologies Corporation
发明人： Chakravarthy Gopalan , Jeffrey Shields , Venkatesh Gopinath , Janet Siao-Yian Wang , Kuei-Chang Tsai
IPC分类号： H01L29/04 , H01L45/00 , H01L21/06 , H01L21/04
CPC分类号： H01L45/08 , H01L21/04 , H01L21/06 , H01L21/76865 , H01L45/065 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/16
摘要： In accordance with an embodiment of the present invention, a resistive switching device includes an opening disposed within a first dielectric layer, a conductive barrier layer disposed on sidewalls of the opening, a fill material including an inert material filling the opening. A solid electrolyte layer is disposed over the opening. The solid electrolyte contacts the fill material but not the conductive barrier layer. A top electrode is disposed over the solid electrolyte.
摘要翻译：根据本发明的实施例，电阻式开关装置包括设置在第一电介质层内的开口，设置在开口侧壁上的导电阻挡层，填充材料，填充材料填充开口。固体电解质层设置在开口上方。固体电解质与填充材料接触，但不与导电阻挡层接触。顶部电极设置在固体电解质上。

3. 发明申请

US20150004778A1 HIGH LINEARITY SOI WAFER FOR LOW-DISTORTION CIRCUIT APPLICATIONS 有权
公开(公告)号：US20150004778A1
公开(公告)日：2015-01-01
申请号：US13929955
申请日：2013-06-28
申请人： International Business Machines Corporation
发明人： ALAN B. BOTULA , Jeffrey E. Hanrahan , Mark D. Jaffe , Alvin J. Joseph , Dale W. Martin , Gerd Pfeiffer , James A. Slinkman
IPC分类号： H01L21/04
CPC分类号： H01L21/76251 , H01L21/04 , H01L21/265 , H01L21/26506 , H01L21/324
摘要： According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing.

4. 发明授权

US08823140B2 GaN vertical bipolar transistor 有权
标题翻译： GaN垂直双极晶体管
公开(公告)号：US08823140B2
公开(公告)日：2014-09-02
申请号：US13675916
申请日：2012-11-13
申请人： Avogy, Inc.
发明人： Hui Nie , Andrew Edwards , Isik Kizilyalli , Dave Bour
IPC分类号： H01L29/66
CPC分类号： H01L21/04 , H01L29/0615 , H01L29/2003 , H01L29/42304 , H01L29/66318 , H01L29/732 , H01L29/7371
摘要： An embodiment of a semiconductor device includes a III-nitride base structure of a first conductivity type, and a III-nitride emitter structure of a second conductivity type having a first surface and a second surface. The second surface is substantially opposite the first surface. The first surface of the III-nitride emitter structure is coupled to a surface of the III-nitride base structure. The semiconductor also includes a first dielectric layer coupled to the second surface of the III-nitride emitter structure, and a spacer coupled to a sidewall of the III-nitride emitter structure and the surface of the III-nitride base structure. The semiconductor also includes a base contact structure with a III-nitride material coupled to the spacer, the surface of the III-nitride base structure, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the base contact structure and the III-nitride emitter structure.
摘要翻译：半导体器件的实施例包括第一导电类型的III族氮化物基底结构和具有第一表面和第二表面的第二导电类型的III族氮化物发射极结构。第二表面基本上与第一表面相对。 III族氮化物发射极结构的第一表面耦合到III族氮化物基底结构的表面。半导体还包括耦合到III族氮化物发射极结构的第二表面的第一电介质层和耦合到III族氮化物发射极结构的侧壁和III族氮化物基底结构的表面的间隔物。该半导体还包括具有连接到间隔物，III族氮化物基底结构的表面和第一介电层的III族氮化物材料的基底接触结构，使得第一介电层和间隔物设置在基底触点结构和III族氮化物发射极结构。

5. 发明申请

US20140110670A1 DOPED GRAPHENE STRUCTURE COMPRISING HYDROPHOBIC ORGANIC MATERIAL, METHOD FOR PREPARING THE SAME, AND TRANSPARENT ELECTRODE, DISPLAY DEVICE AND SOLAR CELL COMPRISING THE ELECTRODE 有权
标题翻译：包含疏水性有机材料的包覆石脑油结构，其制备方法和透明电极，显示装置和包含电极的太阳能电池
公开(公告)号：US20140110670A1
公开(公告)日：2014-04-24
申请号：US13847772
申请日：2013-03-20
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Seon-mi YOON , Hyeon-jin SHIN , Jae-young CHOI , Won-mook CHOI , Soo-min KIM , Young-hee LEE
IPC分类号： H01L29/16 , H01L21/04
CPC分类号： H01L29/1606 , H01G9/20 , H01G9/2022 , H01G9/2077 , H01L21/04 , H01L21/0405 , H01L29/16 , H01L51/0045 , H01L51/442 , H01L51/5203 , Y02E10/50 , Y02E10/542 , Y02E10/549
摘要： A hydrophobic organic layer may be formed on a surface of a graphene doped with a dopant to improve stability of the doped graphene with respect to moisture and temperature. Thus, the transparent electrode having the doped graphene containing the hydrophobic organic layer may be usefully applied in solar cells or display devices.
摘要翻译：可以在掺杂有掺杂剂的石墨烯的表面上形成疏水性有机层，以改善掺杂石墨烯相对于水分和温度的稳定性。因此，具有含有疏水性有机层的掺杂石墨烯的透明电极可以有用地应用于太阳能电池或显示装置。

6. 发明授权

US08697538B1 Method of forming pattern in substrate 有权
标题翻译：在基材中形成图案的方法
公开(公告)号：US08697538B1
公开(公告)日：2014-04-15
申请号：US13670477
申请日：2012-11-07
申请人： Winbond Electronics Corp.
发明人： Lu-Ping Chiang
IPC分类号： H01L21/76 , H01L21/44 , H01L21/311 , H01L21/033 , H01L23/528 , H01L29/06
CPC分类号： H01L21/04 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L23/528 , H01L29/06 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a pattern in a substrate is provided, in which the substrate having a pattern region is provided first. A plurality of stripe-shaped mask layers is formed on the substrate in the pattern region. Each of at least two adjacent stripe-shaped mask layers among the stripe-shaped mask layers has a protrusion portion and the protrusion portions face to each other. A spacer is formed on sidewalls of the stripe-shaped mask layers, wherein a thickness of the spacer is greater than a half of a distance between two of the protrusion portions. Subsequently, the stripe-shaped mask layers are removed. An etching process is performed by using the spacer as a mask to form trenches in the substrate. Thereafter, the trenches are filled with a material.
摘要翻译：提供了一种在基板中形成图案的方法，其中首先提供具有图案区域的基板。在图案区域中的基板上形成多个条形掩模层。条状掩模层中的至少两个相邻的条形掩模层中的每一个具有突出部分，并且突出部分彼此面对。间隔件形成在条形掩模层的侧壁上，其中间隔物的厚度大于两个突出部分之间的距离的一半。随后，去除条形掩模层。通过使用间隔物作为掩模来进行蚀刻工艺，以在衬底中形成沟槽。此后，沟槽被填充材料。

7. 发明申请

US20130307031A1 SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR STRUCTURE, AND METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE 有权
标题翻译：具有半导体结构的半导体结构，半导体器件和制造半导体结构的方法
公开(公告)号：US20130307031A1
公开(公告)日：2013-11-21
申请号：US13472949
申请日：2012-05-16
申请人： Mathias Plappert , Hans-Joachim Schulze
发明人： Mathias Plappert , Hans-Joachim Schulze
IPC分类号： H01L29/772 , H01L21/762 , H01L21/20 , H01L29/02 , H01L29/73
CPC分类号： H01L21/02595 , H01L21/02532 , H01L21/02592 , H01L21/02598 , H01L21/02609 , H01L21/02667 , H01L21/04 , H01L21/187 , H01L21/265 , H01L21/28 , H01L21/324 , H01L29/04 , H01L29/43 , H01L29/7802 , H01L2924/0002 , H01L2924/00
摘要： According to an embodiment, a semiconductor structure includes a first monocrystalline semiconductor portion having a first lattice constant in a reference direction; a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion; and a metal layer formed on and in contact with the second monocrystalline semiconductor portion.
摘要翻译：根据实施例，半导体结构包括在参考方向上具有第一晶格常数的第一单晶半导体部分; 在所述第一单晶半导体部分上具有与所述第一晶格常数不同的参考方向上的第二晶格常数的第二单晶半导体部分; 以及形成在第二单晶半导体部分上并与第二单晶半导体部分接触的金属层。

8. 发明申请

US20130272069A1 3D NON-VOLATILE STORAGE WITH TRANSISTOR DECODING STRUCTURE 有权
标题翻译：具有晶体管解码结构的3D非易失性存储
公开(公告)号：US20130272069A1
公开(公告)日：2013-10-17
申请号：US13733030
申请日：2013-01-02
申请人： SANDISK TECHNOLOGIES INC.
发明人： Peter Rabkin , Masaaki Higashitani
IPC分类号： G11C16/04 , G11C16/08 , G11C16/06
CPC分类号： H01L29/66757 , G11C16/0483 , G11C16/06 , G11C16/08 , H01L21/02532 , H01L21/02595 , H01L21/04 , H01L21/26513 , H01L27/11556 , H01L27/11573 , H01L27/11582 , H01L27/1222 , H01L27/1259 , H01L29/42384 , H01L29/66477 , H01L29/66742 , H01L29/6675 , H01L29/66787 , H01L29/785 , H01L29/78642 , H01L29/78696 , H01L29/7926
摘要： Disclosed herein are 3D stacked memory devices having WL select gates. The 3D stacked memory device could have NAND strings. The WL select gates may be located adjacent to a word line hookup area of a word line plate. The word line plate may be driven by a word line plate driver and may have many word lines. The WL select gates may select individual word lines or groups of word lines. Therefore, smaller units that the entire block may be selected. This may reduce capacitive loading. The WL select gates may include thin film transistors. 3D decoding may be provided in a 3D stacked memory device using the WL select gates.
摘要翻译：这里公开了具有WL选择门的3D堆叠存储器件。 3D堆叠存储器件可以具有NAND串。 WL选择栅极可以位于字线板的字线连接区域附近。字线板可以由字线驱动器驱动，并且可以具有许多字线。 WL选择门可以选择单个字线或字线组。因此，可以选择整个块的较小单元。这可能会降低电容负载。 WL选择栅极可以包括薄膜晶体管。可以使用WL选择门在3D堆叠存储器件中提供3D解码。

9. 发明申请

US20130137253A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130137253A1
公开(公告)日：2013-05-30
申请号：US13705610
申请日：2012-12-05
申请人： Hiroshi KONO , Takashi Shinohe
发明人： Hiroshi KONO , Takashi Shinohe
IPC分类号： H01L21/04
CPC分类号： H01L21/04 , H01L29/0619 , H01L29/0834 , H01L29/0839 , H01L29/1608 , H01L29/66068 , H01L29/7395 , H01L29/7802
摘要： A semiconductor device includes: a silicon carbide substrate having first and second main surfaces; a first silicon carbide layer provided on the first main surface of the silicon carbide substrate; first silicon carbide regions formed on a surface of the first silicon carbide layer; second and third silicon carbide regions formed on respective surfaces of the first silicon carbide regions; a fourth silicon carbide region formed between facing first silicon carbide regions with the first silicon carbide layer therebetween; a gate insulating film formed continuously on surfaces of the first silicon carbide regions, the first silicon carbide layer, and the fourth silicon carbide region; a gate electrode formed on the gate insulating film; an interlayer insulating film covering the gate electrode; a first electrode electrically connected to the second and third silicon carbide regions; and a second electrode formed on the second main surface of the silicon carbide substrate.
摘要翻译：半导体器件包括：具有第一和第二主表面的碳化硅衬底; 设置在所述碳化硅衬底的所述第一主表面上的第一碳化硅层; 第一碳化硅区域形成在第一碳化硅层的表面上; 形成在第一碳化硅区域的相应表面上的第二和第三碳化硅区域; 形成在面对的第一碳化硅区域之间的第四碳化硅区域，其间具有第一碳化硅层; 在第一碳化硅区域，第一碳化硅层和第四碳化硅区域的表面上连续形成的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 覆盖栅电极的层间绝缘膜; 电连接到第二和第三碳化硅区域的第一电极; 以及形成在碳化硅衬底的第二主表面上的第二电极。

10. 发明申请

US20130107620A1 METHODS AND APPARATUSES INCLUDING A SELECT TRANSISTOR HAVING A BODY REGION INCLUDING MONOCRYSTALLINE SEMICONDUCTOR MATERIAL AND/OR AT LEAST A PORTION OF ITS GATE LOCATED IN A SUBSTRATE 有权
公开(公告)号：US20130107620A1
公开(公告)日：2013-05-02
申请号：US13282237
申请日：2011-10-26
申请人： Toru Tanzawa
发明人： Toru Tanzawa
IPC分类号： G11C16/04 , H01L21/04 , H01L21/336
CPC分类号： H01L27/11556 , G11C16/04 , G11C16/0408 , H01L21/04 , H01L27/11524 , H01L27/11551 , H01L29/04 , H01L29/16
摘要： Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatuses and a select transistor coupled to the memory cell string. In at least one of such apparatuses, the select transistor can include a body region including a monocrystalline semiconductor material. Other embodiments including additional apparatuses and methods are described.

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