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1. 发明授权

US09431402B2 Semiconductor device having buried bit line and method for fabricating the same 有权
标题翻译：具有掩埋位线的半导体器件及其制造方法
公开(公告)号：US09431402B2
公开(公告)日：2016-08-30
申请号：US13468091
申请日：2012-05-10
申请人： Yun-Hyuck Ji , Kwan-Woo Do , Beom-Yong Kim , Seung-Mi Lee , Woo-Young Park
发明人： Yun-Hyuck Ji , Kwan-Woo Do , Beom-Yong Kim , Seung-Mi Lee , Woo-Young Park
IPC分类号： H01L21/336 , H01L27/108 , H01L21/20 , H01L29/78 , H01L29/66
CPC分类号： H01L27/10808 , H01L21/2018 , H01L27/10873 , H01L27/10885 , H01L29/66666 , H01L29/7827
摘要： A method for fabricating a semiconductor device includes: forming an insulation layer over a semiconductor substrate; forming a first conductive layer over the insulation layer; forming a plurality of buried bit lines and insulation layer patterns isolated by a plurality of trenches, wherein the plurality of trenches are formed by etching the first conductive layer and the insulation layer; forming a sacrificial layer to gap-fill the trenches; forming a second conductive layer over the buried bit lines and the sacrificial layer; and forming a plurality of pillars over each of the buried bit lines by etching the second conductive layer.
摘要翻译：一种制造半导体器件的方法包括：在半导体衬底上形成绝缘层; 在所述绝缘层上形成第一导电层; 形成由多个沟槽隔离的多个掩埋位线和绝缘层图案，其中所述多个沟槽通过蚀刻所述第一导电层和所述绝缘层而形成; 形成牺牲层以间隙填充沟槽; 在所述掩埋位线和所述牺牲层上形成第二导电层; 以及通过蚀刻所述第二导电层在每个所述掩埋位线上形成多个柱。

2. 发明授权

US09324385B2 Semiconductor device for generating initialization of information in response to a first clock and outputting the initialization information in response to a second clock 有权
标题翻译：半导体装置，用于响应于第一时钟产生信息的初始化，并响应于第二时钟输出初始化信息
公开(公告)号：US09324385B2
公开(公告)日：2016-04-26
申请号：US13448596
申请日：2012-04-17
申请人： Jinyeong Moon
发明人： Jinyeong Moon
IPC分类号： G06F1/00 , G11C7/10 , G11C19/20 , G11C7/20 , G11C11/4072
CPC分类号： G11C7/1021 , G11C7/1039 , G11C7/20 , G11C11/4072
摘要： A semiconductor device includes an initialization information generation unit configured to operate in response to a first clock and generate first initialization information having a value that is adjusted according to a value of an address signal that corresponds to output data, a domain crossing unit configured to receive the first initialization information in response to the first clock and output the first initialization information as second initialization information by outputting the second initialization information in response to a second clock, and a pulse generation unit configured to operate in response to the second clock and adjust a toggling point in time of a control pulse in response to the second initialization information.
摘要翻译：半导体器件包括：初始化信息生成单元，被配置为响应于第一时钟进行操作，并生成具有根据与输出数据对应的地址信号的值进行调整的值的第一初始化信息;域交叉单元，被配置为接收所述第一初始化信息响应于所述第一时钟，并且通过响应于第二时钟输出所述第二初始化信息而将所述第一初始化信息作为第二初始化信息输出，以及脉冲生成单元，被配置为响应于所述第二时钟进行操作并调整响应于第二初始化信息的控制脉冲的切换时间点。

3. 发明授权

US09310430B2 Semiconductor integrated circuit and test control method thereof 有权
标题翻译：半导体集成电路及其测试控制方法
公开(公告)号：US09310430B2
公开(公告)日：2016-04-12
申请号：US13444944
申请日：2012-04-12
申请人： Hong-Sok Choi
发明人： Hong-Sok Choi
IPC分类号： G01R31/00 , G01R31/317
CPC分类号： G01R31/31701
摘要： A semiconductor integrated circuit includes a decoding circuit configured to decode one or more test source signals and generate a plurality of test decoding signals, a transmission circuit configured to transmit the plurality of test decoding signals as a plurality of test mode group signals in response to a test enable signal, wherein the transmission circuit outputs the test mode group signals with maintaining a previous output, when the test decoding signals different from each other are sequentially activated, and a test mode signal output circuit configured to output a plurality of test mode signals corresponding to test mode groups, respectively, in response to the plurality of test mode group signals and one or more test mode select signals.
摘要翻译：半导体集成电路包括：解码电路，被配置为对一个或多个测试源信号进行解码并生成多个测试解码信号;发送电路，被配置为响应于一个测试解码信号，将多个测试解码信号作为多个测试模式组信号测试使能信号，其中当所述测试解码信号彼此不同时，所述传输电路输出所述测试模式组信号并保持先前的输出;以及测试模式信号输出电路，被配置为输出对应的多个测试模式信号以分别响应于多个测试模式组信号和一个或多个测试模式选择信号来测试模式组。

4. 发明授权

US09287283B2 Non-volatile memory device and method for fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US09287283B2
公开(公告)日：2016-03-15
申请号：US13462082
申请日：2012-05-02
申请人： Se-Yun Lim , Eun-Seok Choi , Young-Wook Lee , Won-Joon Choi , Ki-Hong Lee , Sang-Bum Lee
发明人： Se-Yun Lim , Eun-Seok Choi , Young-Wook Lee , Won-Joon Choi , Ki-Hong Lee , Sang-Bum Lee
IPC分类号： H01L27/115
CPC分类号： H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L27/11582
摘要： A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate forming a first material layer over a resulting structure in which the trench is formed, forming a second material layer over the first material layer, removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate, removing the second material layer, and burying a channel layer within the trench in which the second material layer is removed.
摘要翻译：一种用于制造非易失性存储器件的方法包括在衬底上交替堆叠多个层间电介质层和多个导电层，蚀刻层间电介质层和导电层以形成暴露衬底形成表面的沟槽在其中形成沟槽的结果结构上的第一材料层，在第一材料层上形成第二材料层，去除第二材料层的部分和形成在沟槽的底部上的第一材料层，以暴露出衬底，去除第二材料层，以及在去除第二材料层的沟槽内掩埋沟道层。

5. 发明授权

US09269441B2 Method for operating non-volatile memory device 有权
标题翻译：操作非易失性存储器件的方法
公开(公告)号：US09269441B2
公开(公告)日：2016-02-23
申请号：US13353429
申请日：2012-01-19
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： G11C16/06 , G11C16/04 , G11C16/10 , G11C16/34
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3409
摘要： A method for operating a non-volatile memory device includes performing an erase operation onto a memory block including a plurality of memory cells, and performing a first soft program operation onto all the memory cells of a string, after the erase operation, grouping word lines of the string into a plurality of word line groups, and performing a second soft program operation onto memory cells coupled with the word lines of each word line group.
摘要翻译：一种用于操作非易失性存储器件的方法包括在包括多个存储器单元的存储器块上执行擦除操作，并且在擦除操作之后对字符串的所有存储单元执行第一软编程操作，将字线并且对与每个字线组的字线耦合的存储器单元执行第二软编程操作。

6. 发明授权

US09184141B2 Electrostatic discharge protection device 有权
标题翻译：静电放电保护装置
公开(公告)号：US09184141B2
公开(公告)日：2015-11-10
申请号：US12979569
申请日：2010-12-28
申请人： Dong-Ju Lim , Woon-Ha Yim
发明人： Dong-Ju Lim , Woon-Ha Yim
IPC分类号： H01L23/62 , H01L27/02 , H01L29/78
CPC分类号： H01L23/62 , H01L27/027 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection device includes first and second wells of a first conductivity type, the first and second wells having different impurity doping concentrations, respectively, a gate formed on the first well, a source region of a second conductivity type formed at one side of the gate in the first well, a drift region of the second conductivity type formed at the other side of gate and over both of the first well and the second well, and a drain region of the second conductivity type formed in the drift region of the second well.
摘要翻译：静电放电保护装置包括第一导电类型的第一和第二阱，第一和第二阱分别具有不同的杂质掺杂浓度，形成在第一阱上的栅极，形成在第一阱的一侧的第二导电类型的源极区第一阱中的栅极，形成在栅极的另一侧和第一阱和第二阱的另一侧上的第二导电类型的漂移区域以及形成在第一阱和第二阱的漂移区域中的第二导电类型的漏极区域第二口

7. 发明授权

US09058437B2 Semiconductor memory device with high-speed data transmission capability, system having the same, and method for operating the same 有权
公开(公告)号：US09058437B2
公开(公告)日：2015-06-16
申请号：US13548117
申请日：2012-07-12
申请人： Ji-Hyae Bae , Sang-Sik Yoon , Ki-Chang Kwean
发明人： Ji-Hyae Bae , Sang-Sik Yoon , Ki-Chang Kwean
IPC分类号： G06F13/42 , G11C29/10 , G11C29/08 , G11C29/12
CPC分类号： G06F13/4243 , G11C29/08 , G11C29/10 , G11C29/12015
摘要： Semiconductor memory device with high-speed data transmission capability, system having the same includes a plurality of address input circuits and a plurality of data output circuits and a training driver configured to distribute address information input through the plurality of address input circuits together with a data loading signal for a read training, and generate data training patterns to be output through the plurality of data output circuits.

8. 发明授权

US09036392B2 Redundancy circuit for reducing chip area 有权
标题翻译：用于减少芯片面积的冗余电路
公开(公告)号：US09036392B2
公开(公告)日：2015-05-19
申请号：US13207650
申请日：2011-08-11
申请人： Heung-Taek Oh
发明人： Heung-Taek Oh
IPC分类号： G11C17/00 , H03K19/003 , G11C29/00 , G11C17/16
CPC分类号： H03K19/00392 , G11C17/16 , G11C29/787
摘要： A redundancy circuit includes a plurality of block address lines, a first fuse array storing a first data, a plurality of first local lines configured to supply a verification voltage to the first fuse array in response to a signal of a corresponding line among the plurality of block address lines, a second fuse array storing a second data, a plurality of second local lines configured to supply the verification voltage to the second fuse array in response to a signal of a corresponding line among the plurality of block address lines, and a plurality of verification lines configured to check the first data of the first fuse array and the second data of the second fuse array, wherein the plurality of verification lines are shared by the first fuse array and the second fuse array and are disposed between the first fuse array and the second fuse array.
摘要翻译：冗余电路包括多个块地址线，存储第一数据的第一熔丝阵列，多个第一本地线，其被配置为响应于所述第一熔丝阵列中的相应线的信号，向第一熔丝阵列提供验证电压块地址线，存储第二数据的第二熔丝阵列，多个第二本地线，被配置为响应于所述多个块地址线中的对应线的信号而将验证电压提供给所述第二熔丝阵列，以及多个被配置为检查第一熔丝阵列的第一数据和第二熔丝阵列的第二数据的验证线，其中多个验证线由第一熔丝阵列和第二熔丝阵列共享，并且设置在第一熔丝阵列和第二保险丝阵列。

9. 发明授权

US09013072B2 Internal voltage generator and operation method thereof 有权
标题翻译：内部电压发生器及其运行方法
公开(公告)号：US09013072B2
公开(公告)日：2015-04-21
申请号：US13277792
申请日：2011-10-20
申请人： Joo-Yun Ha
发明人： Joo-Yun Ha
IPC分类号： H02J9/00
CPC分类号： H02J9/005 , Y10T307/406 , Y10T307/50
摘要： An internal voltage generation circuit includes a plurality of active driving units configured to supply a plurality of active power supply voltages to a plurality of voltage terminals, respectively, in an active mode, and a common standby driving unit configured to commonly supply a standby power supply voltage to the plurality of voltage terminals in a standby mode.
摘要翻译：内部电压产生电路包括多个有源驱动单元，其被配置为分别在多个电压端子中以主动模式提供多个有功电源电压;以及公共备用驱动单元，其被配置为共同地提供备用电源在待机模式下对多个电压端子施加电压。

10. 发明授权

US08988961B2 Self-refresh control circuit and memory including the same 有权
标题翻译：自刷新控制电路和存储器包括相同的
公开(公告)号：US08988961B2
公开(公告)日：2015-03-24
申请号：US13525885
申请日：2012-06-18
申请人： Jeong-Tae Hwang
发明人： Jeong-Tae Hwang
IPC分类号： G11C7/00 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/40611 , G11C2211/4067
摘要： An self-refresh control circuit for controlling a self-refresh operation of a memory device includes a self-refresh control logic block configured to control the memory device to perform the self-refresh operation and an initial refresh control block configured to activate the self-refresh control logic block in an initialization period of the memory device.
摘要翻译：一种用于控制存储装置的自刷新操作的自刷新控制电路，包括配置成控制存储装置执行自刷新操作的自刷新控制逻辑块，以及配置为启动自刷新操作的初始刷新控制块，在存储器件的初始化期间刷新控制逻辑块。

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