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1. 发明授权

US07898317B2 Circuit for generating negative voltage and a semiconductor memory apparatus using the same 失效
标题翻译：用于产生负电压的电路和使用其的半导体存储装置
公开(公告)号：US07898317B2
公开(公告)日：2011-03-01
申请号：US12347366
申请日：2008-12-31
申请人： Hong-Sok Choi
发明人： Hong-Sok Choi
IPC分类号： G05F1/10
CPC分类号： G11C5/145
摘要： A circuit for generating negative voltage includes a variable period oscillator configured to generate an oscillator signal enabled in response to a detection signal and to determine a period of the oscillator signal in response to a control signal, a pump configured to perform pumping operations in response to the oscillator signal and to generate a negative voltage by the pumping operations, a negative voltage detecting unit configured to detect the level of the negative voltage to generate the detection signal, and a gate-induced drain leakage current detecting unit configured to measure the amount of a gate-induced drain leakage current to generate the control signal.
摘要翻译：用于产生负电压的电路包括可变周期振荡器，其被配置为响应于检测信号产生使能的振荡器信号，并响应于控制信号确定振荡器信号的周期;泵被配置为响应于振荡器信号并通过泵浦操作产生负电压;负电压检测单元，被配置为检测负电压的电平以产生检测信号;栅极引起的漏极泄漏电流检测单元，被配置为测量栅极引起的漏极漏电流产生控制信号。

2. 发明授权

US07705634B2 Input circuit of semiconductor integrated circuit 失效
标题翻译：半导体集成电路的输入电路
公开(公告)号：US07705634B2
公开(公告)日：2010-04-27
申请号：US11964792
申请日：2007-12-27
申请人： Hong-Sok Choi
发明人： Hong-Sok Choi
IPC分类号： H03K5/22
CPC分类号： G11C5/14 , G11C7/22 , G11C7/225
摘要： An input circuit is disclosed. The input circuit can include a cross voltage generating block that can be configured to perform charge-sharing on a pair of input signals whose phases are opposite to each other and generate a cross voltage, and an input buffer block that can be configured to buffer the pair of input signals at a voltage level corresponding to a voltage level of the cross voltage and generate an output signal.
摘要翻译：公开了一种输入电路。输入电路可以包括交叉电压产生块，其可以被配置为在相位彼此相反并产生交叉电压的一对输入信号上执行电荷共享，以及输入缓冲器块，其可被配置为缓冲一对输入信号处于与交叉电压的电压电平对应的电压电平并产生输出信号。

3. 发明申请

US20100244882A1 Burn-In Test Method and System 审中-公开
标题翻译：老化测试方法和系统
公开(公告)号：US20100244882A1
公开(公告)日：2010-09-30
申请号：US12486268
申请日：2009-06-17
申请人： Hong-Sok Choi
发明人： Hong-Sok Choi
IPC分类号： G01R31/26
CPC分类号： G11C29/06 , G11C29/02 , G11C29/025 , G11C2029/1202
摘要： A method for performing a burn-in test of a metal wire for a signal transmission of a semiconductor device including driving a first terminal of the metal wire with a first voltage and forming a current path in the metal wire by driving a second terminal of the metal wire with a second voltage whose level is different from that of the first voltage.
摘要翻译：一种执行用于半导体器件的信号传输的金属线的老化测试的方法，包括：用第一电压驱动金属线的第一端，并通过驱动金属线的第二端，形成金属线中的电流路径金属线具有与第一电压的电平不同的第二电压。

4. 发明申请

US20090002051A1 INPUT CIRCUIT OF SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：半导体集成电路的输入电路
公开(公告)号：US20090002051A1
公开(公告)日：2009-01-01
申请号：US11964792
申请日：2007-12-27
申请人： Hong-Sok Choi
发明人： Hong-Sok Choi
IPC分类号： H03L5/00
CPC分类号： G11C5/14 , G11C7/22 , G11C7/225
摘要： An input circuit is disclosed. The input circuit can include a cross voltage generating block that can be configured to perform charge-sharing on a pair of input signals whose phases are opposite to each other and generate a cross voltage, and an input buffer block that can be configured to buffer the pair of input signals at a voltage level corresponding to a voltage level of the cross voltage and generate an output signal.
摘要翻译：公开了一种输入电路。输入电路可以包括交叉电压产生块，其可以被配置为在相位彼此相反并产生交叉电压的一对输入信号上执行电荷共享，以及输入缓冲器块，其可被配置为缓冲一对输入信号处于与交叉电压的电压电平对应的电压电平并产生输出信号。

5. 发明授权

US6060930A Delay circuit 失效
标题翻译：延时电路
公开(公告)号：US6060930A
公开(公告)日：2000-05-09
申请号：US8328
申请日：1998-01-16
申请人： Hong-Sok Choi
发明人： Hong-Sok Choi
IPC分类号： H03K19/00 , H03K5/00 , H03K5/13
CPC分类号： H03K5/13 , H03K2005/00045 , H03K2005/00084 , H03K2005/0028
摘要： A delay circuit which is capable of maintaining a constant delay time. The circuit includes a plurality of first delay circuits connected in series and each having an inverter for inverting an input voltage signal, and a variable capacitor connected to an output terminal of the inverter.
摘要翻译：一种能够保持恒定的延迟时间的延迟电路。电路包括串联连接的多个第一延迟电路，每个具有用于反相输入电压信号的反相器和连接到反相器的输出端子的可变电容器。

6. 发明授权

US09310430B2 Semiconductor integrated circuit and test control method thereof 有权
标题翻译：半导体集成电路及其测试控制方法
公开(公告)号：US09310430B2
公开(公告)日：2016-04-12
申请号：US13444944
申请日：2012-04-12
申请人： Hong-Sok Choi
发明人： Hong-Sok Choi
IPC分类号： G01R31/00 , G01R31/317
CPC分类号： G01R31/31701
摘要： A semiconductor integrated circuit includes a decoding circuit configured to decode one or more test source signals and generate a plurality of test decoding signals, a transmission circuit configured to transmit the plurality of test decoding signals as a plurality of test mode group signals in response to a test enable signal, wherein the transmission circuit outputs the test mode group signals with maintaining a previous output, when the test decoding signals different from each other are sequentially activated, and a test mode signal output circuit configured to output a plurality of test mode signals corresponding to test mode groups, respectively, in response to the plurality of test mode group signals and one or more test mode select signals.
摘要翻译：半导体集成电路包括：解码电路，被配置为对一个或多个测试源信号进行解码并生成多个测试解码信号;发送电路，被配置为响应于一个测试解码信号，将多个测试解码信号作为多个测试模式组信号测试使能信号，其中当所述测试解码信号彼此不同时，所述传输电路输出所述测试模式组信号并保持先前的输出;以及测试模式信号输出电路，被配置为输出对应的多个测试模式信号以分别响应于多个测试模式组信号和一个或多个测试模式选择信号来测试模式组。

7. 发明授权

US07904742B2 Local skew detecting circuit for semiconductor memory apparatus 有权
标题翻译：半导体存储装置局部偏斜检测电路
公开(公告)号：US07904742B2
公开(公告)日：2011-03-08
申请号：US11963166
申请日：2007-12-21
申请人： Hong-Sok Choi
发明人： Hong-Sok Choi
IPC分类号： G06F1/00 , H03K19/00 , H03L7/00 , G11C5/06 , G11C21/00 , G06F12/00 , G06F17/50
CPC分类号： H03K5/26 , G11C7/22 , G11C7/222 , G11C29/02 , G11C29/025 , G11C29/12015 , G11C29/50 , G11C29/50012 , G11C2207/2254
摘要： A local skew detecting circuit for a semiconductor integrated circuit includes a reference delay block that receives a test signal and generates a reference delay signal by delaying the test signal by a predetermined delay time, and a first timing detecting block coupled with the reference delay block, the first timing detecting block configured to receive the test signal, generate a first delay signal by delaying the test signal by the same predetermined delay time, and detect an enable timing order of the reference delay signal and the first delay signal to generate a first detection signal.
摘要翻译：用于半导体集成电路的局部偏斜检测电路包括参考延迟块，其接收测试信号并通过将测试信号延迟预定的延迟时间而产生参考延迟信号，以及与参考延迟块耦合的第一定时检测块，所述第一定时检测块被配置为接收所述测试信号，通过将所述测试信号延迟相同的预定延迟时间来产生第一延迟信号，并且检测所述参考延迟信号和所述第一延迟信号的使能定时顺序以产生第一检测信号。

8. 发明申请

US20090015307A1 LOCAL SKEW DETECTING CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：用于半导体存储器的局部检测电路
公开(公告)号：US20090015307A1
公开(公告)日：2009-01-15
申请号：US11963166
申请日：2007-12-21
申请人： Hong-Sok Choi
发明人： Hong-Sok Choi
IPC分类号： H03H11/26 , H03K3/037
CPC分类号： H03K5/26 , G11C7/22 , G11C7/222 , G11C29/02 , G11C29/025 , G11C29/12015 , G11C29/50 , G11C29/50012 , G11C2207/2254
摘要： A local skew detecting circuit for a semiconductor integrated circuit includes a reference delay block that receives a test signal and generates a reference delay signal by delaying the test signal by a predetermineddelay time, and a first timing detecting block coupled with the reference delay block, the first timing detecting block configured to receive the test signal, generate a first delay signal by delaying the test signal by the same predetermined delay time, and detect an enable timing order of the reference delay signal and the first delay signal to generate a first detection signal.
摘要翻译：用于半导体集成电路的局部偏斜检测电路包括参考延迟块，其接收测试信号并通过将测试信号延迟预定的延迟时间并产生参考延迟信号，以及与参考延迟块耦合的第一定时检测块，第一定时检测块，被配置为接收测试信号，通过将测试信号延迟相同的预定延迟时间来产生第一延迟信号，并且检测参考延迟信号和第一延迟信号的使能定时顺序以产生第一检测信号。

9. 发明申请

US20080192562A1 CIRCUIT AND METHOD FOR DECODING COLUMN ADDRESSES IN SEMICONDUCTOR MEMORY APPARATUS 失效
标题翻译：用于解码半导体存储器装置中的色谱柱的电路和方法
公开(公告)号：US20080192562A1
公开(公告)日：2008-08-14
申请号：US11961998
申请日：2007-12-20
申请人： Hong-Sok Choi
发明人： Hong-Sok Choi
IPC分类号： G11C8/00
CPC分类号： G11C29/34 , G11C2029/1204 , G11C2029/1802 , G11C2029/2602
摘要： A column address decoding circuit of a semiconductor memory apparatus includes a predecoder configured to combine a column address and a decoding test signal, thereby outputting a decoding address. A main decoder receives the decoding address, thereby outputting a plurality of column select signals.
摘要翻译：半导体存储装置的列地址解码电路包括：预解码器，被配置为组合列地址和解码测试信号，从而输出解码地址。主解码器接收解码地址，从而输出多个列选择信号。

10. 发明授权

US08102722B2 Data output device for semiconductor memory apparatus 有权
标题翻译：半导体存储装置的数据输出装置
公开(公告)号：US08102722B2
公开(公告)日：2012-01-24
申请号：US12494377
申请日：2009-06-30
申请人： Hong-Sok Choi
发明人： Hong-Sok Choi
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/02 , G11C7/1057 , G11C7/22 , G11C7/222
摘要： A data output device of a semiconductor memory apparatus includes detection means configured to detect a specified operation frequency range; pre-driving means configured to be inputted with signals; driving means configured to receive outputs of the pre-driving means and drive an output of data; and adjustment means configured to adjust a slew rate of the driving means under the control of an output signal of the detection means.
摘要翻译：半导体存储装置的数据输出装置包括：检测装置，被配置为检测规定的工作频率范围; 配置为输入信号的预驱动装置; 驱动装置，被配置为接收所述预驱动装置的输出并驱动数据的输出; 以及调整装置，被配置为在检测装置的输出信号的控制下调节驱动装置的转换速率。

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