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1. 发明授权

US09036392B2 Redundancy circuit for reducing chip area 有权
标题翻译：用于减少芯片面积的冗余电路
公开(公告)号：US09036392B2
公开(公告)日：2015-05-19
申请号：US13207650
申请日：2011-08-11
申请人： Heung-Taek Oh
发明人： Heung-Taek Oh
IPC分类号： G11C17/00 , H03K19/003 , G11C29/00 , G11C17/16
CPC分类号： H03K19/00392 , G11C17/16 , G11C29/787
摘要： A redundancy circuit includes a plurality of block address lines, a first fuse array storing a first data, a plurality of first local lines configured to supply a verification voltage to the first fuse array in response to a signal of a corresponding line among the plurality of block address lines, a second fuse array storing a second data, a plurality of second local lines configured to supply the verification voltage to the second fuse array in response to a signal of a corresponding line among the plurality of block address lines, and a plurality of verification lines configured to check the first data of the first fuse array and the second data of the second fuse array, wherein the plurality of verification lines are shared by the first fuse array and the second fuse array and are disposed between the first fuse array and the second fuse array.
摘要翻译：冗余电路包括多个块地址线，存储第一数据的第一熔丝阵列，多个第一本地线，其被配置为响应于所述第一熔丝阵列中的相应线的信号，向第一熔丝阵列提供验证电压块地址线，存储第二数据的第二熔丝阵列，多个第二本地线，被配置为响应于所述多个块地址线中的对应线的信号而将验证电压提供给所述第二熔丝阵列，以及多个被配置为检查第一熔丝阵列的第一数据和第二熔丝阵列的第二数据的验证线，其中多个验证线由第一熔丝阵列和第二熔丝阵列共享，并且设置在第一熔丝阵列和第二保险丝阵列。

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