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1. 发明授权

US07122473B2 Edge and bevel cleaning process and system 有权
标题翻译：边缘和斜面清洁过程和系统
公开(公告)号：US07122473B2
公开(公告)日：2006-10-17
申请号：US10920028
申请日：2004-08-16
申请人： Jalal Ashjaee , Rimma Volodarsky , Cyprian E. Uzoh , Bulent M. Basol , Homayoun Talieh
发明人： Jalal Ashjaee , Rimma Volodarsky , Cyprian E. Uzoh , Bulent M. Basol , Homayoun Talieh
IPC分类号： H01L21/445
CPC分类号： H01L21/6708 , H01L21/2885 , H01L21/32134
摘要： The present invention provides at least one nozzle that sprays a rotating workpiece with an etchant at an edge thereof. The at least one nozzle is located in an upper chamber of a vertically configured processing subsystem that also includes mechanisms for plating, cleaning and drying in upper and lower chambers.
摘要翻译：本发明提供了至少一个喷嘴，其在其边缘处用蚀刻剂喷射旋转的工件。至少一个喷嘴位于垂直配置的处理子系统的上部室中，其还包括用于上部和下部室中的电镀，清洁和干燥的机构。

2. 发明授权

US07115510B2 Method for electrochemically processing a workpiece 有权
标题翻译：电化学处理工件的方法
公开(公告)号：US07115510B2
公开(公告)日：2006-10-03
申请号：US10996164
申请日：2004-11-22
申请人： Bulent M. Basol , Homayoun Talieh , Cyprian E. Uzoh
发明人： Bulent M. Basol , Homayoun Talieh , Cyprian E. Uzoh
IPC分类号： H01L21/44
CPC分类号： B23H5/08 , C25D5/02 , C25D5/10 , C25D5/18 , C25D5/22 , C25D7/123 , H01L21/2885 , H01L21/32125 , H01L21/7684 , H01L21/76877
摘要： The present invention relates to a process for forming a near-planar or planar layer of a conducting material, such as copper, on a surface of a workpiece using an ECMPR technique. The process preferably uses at least two separate plating solution chemistries to form a near-planar or planar copper layer on a semiconductor substrate that has features or cavities on its surface.
摘要翻译：本发明涉及使用ECMPR技术在工件表面上形成诸如铜的导电材料的近平面或平面层的方法。该方法优选使用至少两个单独的电镀溶液化学物质在其表面上具有特征或空腔的半导体衬底上形成近平面或平面的铜层。

3. 发明授权

US06921551B2 Plating method and apparatus for controlling deposition on predetermined portions of a workpiece 有权
公开(公告)号：US06921551B2
公开(公告)日：2005-07-26
申请号：US09961193
申请日：2001-09-20
申请人： Bulent M. Basol
发明人： Bulent M. Basol
IPC分类号： C25D5/02 , C25D5/08 , C25D5/18 , C25D5/22 , C25D5/34 , C25D7/12 , C25D17/00 , C25D21/00 , H01L21/288 , H01L21/3205 , H01L21/768 , H01L23/12 , C23C18/00 , C23C14/00
CPC分类号： H01L21/76879 , C25D5/06 , C25D5/10 , C25D5/22 , C25D5/34 , C25D7/123 , C25D17/001 , H01L21/2885 , H01L21/7684 , H01L21/76877 , Y10T428/24562
摘要： The present invention relates to methods and apparatus for plating a conductive material on a workpiece surface in a highly desirable manner. Using a workpiece-surface-influencing device, such as a mask or sweeper, that preferentially contacts the top surface of the workpiece, relative movement between the workpiece and the workpiece-surface-influencing device is established so that an additive in the electrolyte solution disposed on the workpiece and which is adsorbed onto the top surface is removed or otherwise its amount or concentration changed with respect to the additive on the cavity surface of the workpiece. Plating of the conductive material can place prior to, during and after usage of the workpiece-surface-influencing device, particularly after the workpiece surface influencing device no longer contacts any portion of the top surface of the workpiece, to achieve desirable semiconductor structures.

4. 发明授权

US06857947B2 Advanced chemical mechanical polishing system with smart endpoint detection 失效
标题翻译：先进的化学机械抛光系统，智能端点检测
公开(公告)号：US06857947B2
公开(公告)日：2005-02-22
申请号：US10346425
申请日：2003-01-17
申请人： Yuchun Wang , Bernard M. Frey , Bulent M. Basol , Homayoun Talieh , Douglas W. Young , Brett E. McGrath , Mukesh Desai , Efrain Velazquez , Tuan Truong
发明人： Yuchun Wang , Bernard M. Frey , Bulent M. Basol , Homayoun Talieh , Douglas W. Young , Brett E. McGrath , Mukesh Desai , Efrain Velazquez , Tuan Truong
IPC分类号： B24B21/04 , B24B21/08 , B24B37/013 , B24B37/20 , B24B49/10 , B24B49/16 , B24B21/00
CPC分类号： B24B37/013 , B24B21/04 , B24B21/08 , B24B37/205 , B24B49/10 , B24B49/16
摘要： An apparatus for polishing a workpiece includes a workpiece holder configured to hold the workpiece, a polishing member configured to be positioned adjacent to a face of the workpiece in order to polish the workpiece face with a front side of the polishing member, and a platen having a plurality of pressure zones configured to selectively apply pressure to the polishing member thereby causing the polishing member to contact the workpiece face with selective pressure. In another embodiment, the apparatus includes a pressure controller coupled to the platen and configured to selectively adjust the pressure zones.
摘要翻译：一种用于抛光工件的装置包括：被配置为保持工件的工件保持器;抛光构件，其构造成邻近工件的表面定位，以便抛光工件面与抛光构件的前侧;以及压板，多个压力区被配置为选择性地向抛光构件施加压力，从而使抛光构件与选择压力接触工件面。在另一个实施例中，该装置包括耦合到压板并配置成选择性地调节压力区的压力控制器。

5. 发明授权

US06852630B2 Electroetching process and system 有权
标题翻译：电蚀过程和系统
公开(公告)号：US06852630B2
公开(公告)日：2005-02-08
申请号：US09841622
申请日：2001-04-23
申请人： Bulent M. Basol , Cyprian Uzoh , Halit N. Yakupoglu , Homayoun Talieh
发明人： Bulent M. Basol , Cyprian Uzoh , Halit N. Yakupoglu , Homayoun Talieh
IPC分类号： B23H5/08 , C25F3/14 , H01L21/288 , H01L21/321 , H01L21/3213 , H01L21/768 , H01L21/302
CPC分类号： H01L21/32115 , B23H5/08 , C25F3/14 , H01L21/2885 , H01L21/32134 , H01L21/7684
摘要： A system for optionally depositing or etching a layer of a wafer includes mask plate opposed to the wafer with the mask plate having a plurality of openings that transport a solution to the wafer. An electrode assembly has a first electrode member and a second electrode member having channels that operatively interface a peripheral and center part of the wafer. The channels transport the solution to the mask.
摘要翻译：用于可选地沉积或蚀刻晶片层的系统包括与晶片相对的掩模板，掩模板具有将溶液输送到晶片的多个开口。电极组件具有第一电极部件和第二电极部件，该第二电极部件具有可操作地与晶片的周边部分和中心部分接合的通道。通道将解决方案传输到面罩。

6. 发明授权

US07625814B2 Filling deep features with conductors in semiconductor manufacturing 有权
标题翻译：在半导体制造中填充导体的深层特征
公开(公告)号：US07625814B2
公开(公告)日：2009-12-01
申请号：US11742302
申请日：2007-04-30
申请人： Ismail Emesh , Chantal J. Arena , Bulent M. Basol
发明人： Ismail Emesh , Chantal J. Arena , Bulent M. Basol
IPC分类号： H01L21/338 , H01L21/8234 , H01L21/8244 , H01L21/44
CPC分类号： H01L21/76898 , H01L21/288
摘要： A method of filling a conductive material in a three dimensional integration feature formed on a surface of a wafer is disclosed. The feature is optionally lined with dielectric and/or adhesion/barrier layers and then filled with a liquid mixture containing conductive precursor, such as a solution with dissolved ruthenium precursor or a dispersion or suspension with conductive particles (e.g., gold, silver, copper), and the substrate is rotated while the mixture is on its surface. Then, the liquid carrier is dried from the feature, leaving a conductive layer in the feature. These two steps are optionally repeated until the feature is filled up with the conductor. Then, the conductor is annealed in the feature, thereby forming a dense conductive plug in the feature.
摘要翻译：公开了一种在晶片表面形成的三维积分特征中填充导电材料的方法。该特征可选地包含电介质和/或粘附/阻挡层，然后填充含有导电前体的液体混合物，例如具有溶解的钌前体的溶液或具有导电颗粒（例如金，银，铜）的分散体或悬浮液，并且当混合物在其表面上时基板旋转。然后，从特征中干燥液体载体，在该特征中留下导电层。可选地重复这两个步骤，直到特征被导体填满。然后，导体在特征中退火，从而在该特征中形成致密的导电插塞。

7. 发明申请

US20090065365A1 METHOD AND APPARATUS FOR COPPER ELECTROPLATING 审中-公开
标题翻译：铜电镀的方法和装置
公开(公告)号：US20090065365A1
公开(公告)日：2009-03-12
申请号：US11853174
申请日：2007-09-11
申请人： Ayse Durmus , Ismail Emesh
发明人： Ayse Durmus , Ismail Emesh
IPC分类号： C23C28/02 , C25D17/00
CPC分类号： C25D5/02 , C25D3/38 , C25D17/00
摘要： A method and apparatus for a copper electroplating procedure, wherein a first additive is preferentially adsorbed onto the field region of a substrate and a second additive is preferentially adsorbed onto the surfaces of at least one recessed region of the substrate, is provided. The first additive is more resistive to the electrodeposition relative to the second additive such that the recessed regions are filled at a faster rate than a layer is deposited on the field region.
摘要翻译：一种铜电镀工艺的方法和装置，其中第一添加剂被优先吸附到衬底的场区上，并且第二添加剂被优先吸附到衬底的至少一个凹陷区域的表面上。第一添加剂相对于第二添加剂对电沉积具有更大的阻力，使得凹陷区域以比沉积在场区域上的层更快的速率被填充。

8. 发明申请

US20070131563A1 MEANS TO IMPROVE CENTER TO EDGE UNIFORMITY OF ELECTROCHEMICAL MECHANICAL PROCESSING OF WORKPIECE SURFACE 审中-公开
标题翻译：改善中心工作面电化学机械加工边缘均匀性的手段
公开(公告)号：US20070131563A1
公开(公告)日：2007-06-14
申请号：US11564242
申请日：2006-11-28
申请人： Jeffrey Bogart , Bulent Basol
发明人： Jeffrey Bogart , Bulent Basol
IPC分类号： B23H3/00
CPC分类号： B23H5/08 , C25D5/06 , C25D17/001 , C25D17/06 , C25D17/14 , H01L21/2885 , H01L21/7684 , H01L21/76877
摘要： An electrochemical mechanical process for electroplating or electropolishing a conductive surface of a wafer is provided. The conductive surface of the wafer is touched by a polishing surface of a compressible pad while a process solution flows through the pad and a potential difference is maintained between the conductive surface and an electrode. The pressure between the polishing surface and a central region of the conductive surface is increased by applying a shaping process to either the conductive surface or the pad.
摘要翻译：提供了用于电镀或电抛光晶片的导电表面的电化学机械工艺。当处理液流过焊盘时，晶片的导电表面被可压缩焊盘的抛光表面接触，并且在导电表面和电极之间保持电位差。抛光表面和导电表面的中心区域之间的压力通过对导电表面或焊盘施加成型工艺而增加。

9. 发明授权

US06974769B2 Conductive structure fabrication process using novel layered structure and conductive structure fabricated thereby for use in multi-level metallization 失效
标题翻译：导电结构制造工艺使用新颖的层状结构和导电结构，由此制成，用于多层次金属化
公开(公告)号：US06974769B2
公开(公告)日：2005-12-13
申请号：US10663318
申请日：2003-09-16
申请人： Bulent Basol , Homayoun Talieh , Cyprian Uzoh
发明人： Bulent Basol , Homayoun Talieh , Cyprian Uzoh
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/7684
摘要： Conductive structures in features of an insulator layer on a substrate are fabricated by a particular process. In this process, a layer of conductive material is applied over the insulator layer so that the layer of conductive material covers field regions adjacent the features and fills in the features themselves. A grain size differential between the conductive material which covers the field regions and the conductive material which fills in the features is then established by annealing the layer of conductive material. Excess conductive material is then removed to uncover the field regions and leave the conductive structures. The layer of conductive material is applied so as to define a first layer thickness over the field regions and a second layer thickness in and over the features. These thicknesses are dimensioned such that d1≦0.5d2, with d1 being the first layer thickness and d2 being the second layer thickness. Preferably, the first and second layer thicknesses are dimensioned such that d1≦0.3d2.
摘要翻译：通过特定的工艺制造衬底上的绝缘体层的特征的导电结构。在该过程中，将导电材料层施加在绝缘体层上，使得导电材料层覆盖与特征相邻的场区域并填充特征本身。然后通过退火导电材料层来建立覆盖场区的导电材料与填充特征的导电材料之间的晶粒尺寸差。然后去除过量的导电材料以露出场区并留下导电结构。施加导电材料层以在场区域上限定第一层厚度，并且在特征中和之上限定第二层厚度。这些厚度的尺寸使得其中d 1是第一层厚度，d 2 <2 < / SUB>为第二层厚度。优选地，第一层厚度和第二层厚度的尺寸被确定为使得d 1 = 0.3D 2。

10. 发明授权

US06969456B2 Method of using vertically configured chamber used for multiple processes 有权
标题翻译：使用垂直配置的室用于多个过程的方法
公开(公告)号：US06969456B2
公开(公告)日：2005-11-29
申请号：US10041029
申请日：2001-12-28
申请人： Konstantin Volodarsky , Boguslaw A. Nagorski , Rimma Volodarsky , Douglas W. Young , Cyprian Uzoh , Homayoun Talieh
发明人： Konstantin Volodarsky , Boguslaw A. Nagorski , Rimma Volodarsky , Douglas W. Young , Cyprian Uzoh , Homayoun Talieh
IPC分类号： C25D7/12 , H01L21/00 , H01L21/02 , H01L21/3063 , C25F3/00 , B08B3/04
CPC分类号： H01L21/6719 , C25D7/12 , C25D17/001 , H01L21/67028 , Y10S134/902
摘要： The present invention relates to a containment chamber that is used for carrying out multiple processing steps such as depositing on, polishing, etching, modifying, rinsing, cleaning, and drying a surface on the workpiece. In one example of the present invention, the chamber is used to electro chemically mechanically deposit a conductive material on a semiconductor wafer. The same containment chamber can then be used to rinse and clean the same wafer. As a result, the present invention eliminates the need for separate processing stations for depositing the conductive material and cleaning the wafer. Thus, with the present invention, costs and physical space are reduced while providing an efficient apparatus and method for carrying out multiple processes on the wafer surface using a containment chamber.
摘要翻译：本发明涉及一种用于进行多个处理步骤的容纳室，例如沉积，抛光，蚀刻，改性，漂洗，清洁和干燥工件上的表面。在本发明的一个实例中，室用于在半导体晶片上化学机械地沉积导电材料。然后可以使用相同的容纳室来冲洗和清洁相同的晶片。结果，本发明消除了对用于沉积导电材料和清洁晶片的单独处理站的需要。因此，利用本发明，降低了成本和物理空间，同时提供了使用容纳室在晶片表面上执行多个工艺的有效的装置和方法。

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