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81. 发明申请

US20130194015A1 METHOD FOR THE OPERATION OF ELECTROSTATIC PRECIPITATORS 有权
标题翻译：静电抑制器操作方法
公开(公告)号：US20130194015A1
公开(公告)日：2013-08-01
申请号：US13701055
申请日：2011-06-17
申请人： Per Ranstad , Jögen Linner , Jürgen Biela , Thiago Batista Soeiro
发明人： Per Ranstad , Jögen Linner , Jürgen Biela , Thiago Batista Soeiro
IPC分类号： H03K3/36
CPC分类号： H03K3/36 , H02M7/493
摘要： The disclosure relates to a method for the scheduling and/or the operation of a system of at least two power supplies (11) providing DC pulses to a consumer (5), typically an electrostatic precipitator, wherein the power supplies (11) are energised by a common feeding (1). According to the proposed method one power supply (11) is defined to be the reference power supply, and the initial pulses of each further power supply (11) are shifted by controlled delays (δPri) with respect to the pulses of the reference power supply so as to fill the gaps between the pulses of the reference power supply by the pulses of the further power supplies (11).
摘要翻译：本公开涉及一种用于调度和/或操作至少两个电源（11）的系统的方法，所述电源（11）向消费者（5）（通常为静电除尘器）提供DC脉冲，其中电源（11）被通电通过共同喂养（1）。根据所提出的方法，一个电源（11）被定义为参考电源，并且每个另外的电源（11）的初始脉冲相对于参考电源的脉冲移动受控延迟（deltaPri）以便通过另外的电源（11）的脉冲来填充参考电源的脉冲之间的间隙。

82. 发明申请

US20130082789A1 OSCILLATION CIRCUIT AND OPERATING CURRENT CONTROL METHOD THEREOF 有权
标题翻译：振荡电路及其工作电流控制方法
公开(公告)号：US20130082789A1
公开(公告)日：2013-04-04
申请号：US13704367
申请日：2011-05-10
申请人： Fumihiro Inoue
发明人： Fumihiro Inoue
IPC分类号： H03K3/36
CPC分类号： H03K3/36 , H03K3/011 , H03K3/0231
摘要： An oscillation circuit includes a condenser, a charging/discharging part configured to switch between charging and discharging of the condenser according to a control signal, a comparator configured to compare a voltage of the condenser with a reference voltage and output a comparison result signal, a flip-flop configured to be set or reset according to the comparison result signal, supply an output signal as the control signal to the charging/discharging part, and output the output signal as an oscillation signal, and a current control part configured to control an operating current of the comparator in correspondence with the voltage of the condenser.
摘要翻译：振荡电路包括：冷凝器，配置成根据控制信号在电容器的充电和放电之间切换的充电/放电部，比较器，用于将电容器的电压与参考电压进行比较，并输出比较结果信号; 触发器被配置为根据比较结果信号被设置或复位，将输出信号作为控制信号提供给充电/放电部分，并输出作为振荡信号的输出信号;以及电流控制部分，被配置为控制比较器的工作电流与冷凝器的电压相对应。

83. 发明申请

US20100182094A1 CONSTANT CURRENT DRIVEN OSCILLATING CIRCUIT 有权
标题翻译：恒定电流驱动振荡电路
公开(公告)号：US20100182094A1
公开(公告)日：2010-07-22
申请号：US12683531
申请日：2010-01-07
申请人： Kouji NASU
发明人： Kouji NASU
IPC分类号： H03K3/36
CPC分类号： H03B5/366
摘要： There is provided a constant current driven oscillating circuit including: an oscillator with first and second ends; a first field effect transistor that turns ON when a signal of a lower level than a first threshold voltage is input to a first gate terminal, and outputs, from a second terminal, current that has been input from a first terminal; a second field effect transistor turning ON when a signal output from the oscillator and is at a higher level than a second threshold voltage is input to a second gate terminal connected to the second end of the oscillator, and outputs, from a fourth terminal, current that has been input from a third terminal connected to the second terminal and to the first end of the oscillator; and an adjusting section that adjusts the first threshold voltage according to the level of the signal output from the oscillator.
摘要翻译：提供了一种恒流驱动振荡电路，包括：具有第一和第二端的振荡器; 当第一栅极端子输入低于第一阈值电压的信号时，将第一场效应晶体管导通，并从第二端子输出从第一端子输入的电流; 当从振荡器输出的信号处于比第二阈值电压高的信号时，第二场效应晶体管导通到连接到振荡器的第二端的第二栅极端子，并从第四端子输出电流已从连接到第二终端的第三终端和振荡器的第一端输入; 以及调整部，其根据从振荡器输出的信号的电平来调整第一阈值电压。

84. 发明申请

US20100013567A1 SWITCHING CAPACITOR GENERATION CIRCUIT 审中-公开
公开(公告)号：US20100013567A1
公开(公告)日：2010-01-21
申请号：US12562107
申请日：2009-09-17
申请人： Kazuhiro TOMITA
发明人： Kazuhiro TOMITA
IPC分类号： H03K3/36
CPC分类号： H03B5/04 , H03H19/004
摘要： A switching capacitor generation circuit which reduces the on-resistance and parasitic capacitance of a switch element and improves the operation properties of the switch element. The switching capacitor generation circuit, which has first and second output terminals, includes a first capacitor coupled to the first output terminal, a second capacitor coupled to the second output terminal, and a single switch element coupled between the first and the second capacitors.

85. 发明授权

US07193486B2 Tunable, maximum power output, frequency harmonic comb generator 有权
标题翻译：可调谐，最大功率输出，频率谐波梳发生器
公开(公告)号：US07193486B2
公开(公告)日：2007-03-20
申请号：US11038354
申请日：2005-01-19
申请人： Eric M. Mrozek , Flavia S. Fong , Mark Kintis
发明人： Eric M. Mrozek , Flavia S. Fong , Mark Kintis
IPC分类号： H03K3/36 , H03K3/00
CPC分类号： H03K5/12 , H03B25/00
摘要： A comb frequency generator that is tunable to vary the width of the pulses in the output signal and achieve a maximum power output at different harmonic frequencies. A wavefront compression device receives a sinusoidal input signal and provides wavefront compression to create a compressed signal having a series of periodic fast edges. A delay device receives the fast-edge compressed signal and delays the fast-edge signal to create a delayed fast-edge signal. A combining device receives the original fast-edge compressed signal and the delayed fast-edge compressed signal to generate an output signal including a series of pulses having a width determined by the delay of the delayed signal. In one embodiment, the delay device is a shorted transmission line stub having a length selectively set by a series of MEM devices. In another embodiment, the delay device is an NLTL variable time delay device that delays the fast-edge signal.
摘要翻译：梳状频率发生器，可调谐以改变输出信号中的脉冲宽度，并实现不同谐波频率下的最大功率输出。波前压缩装置接收正弦输入信号并提供波前压缩以产生具有一系列周期性快速边缘的压缩信号。延迟装置接收快速边缘压缩信号并延迟快速边缘信号以产生延迟的快速边缘信号。组合装置接收原始快速边缘压缩信号和延迟的快速边缘压缩信号，以产生包括具有由延迟信号的延迟确定的宽度的一系列脉冲的输出信号。在一个实施例中，延迟装置是具有由一系列MEM装置选择性地设置的长度的短路传输线短截线。在另一个实施例中，延迟装置是延迟快速边缘信号的NLTL可变时间延迟装置。

86. 发明授权

US07113013B2 Pulse generating circuit and sampling circuit 失效
标题翻译：脉冲发生电路和采样电路
公开(公告)号：US07113013B2
公开(公告)日：2006-09-26
申请号：US11136324
申请日：2005-05-24
申请人： Akihiro Kawata
发明人： Akihiro Kawata
IPC分类号： H03K5/01 , H03K3/02 , H03K3/36
CPC分类号： H03K3/33 , H03K17/74
摘要： There is provided a pulse generating circuit, which generates two pulses having a sign of amplitude different from each other, including: a step recovery diode of which electric potential of an anode and a cathode is respectively output as the pulses; a bias unit operable to select either a forward bias or a backward bias according to a given control signal and apply the selected bias to the step recovery diode; a forward current source operable to prescribe a forward current to be supplied to the step recovery diode when the forward bias is applied to the step recovery diode; and a backward current source operable to prescribe a backward current to be supplied to the step recovery diode when the backward bias is applied to the step recovery diode.
摘要翻译：提供脉冲发生电路，其生成具有彼此不同的振幅符号的两个脉冲，包括：分别输出阳极和阴极的电位作为脉冲的阶跃恢复二极管; 偏置单元，用于根据给定的控制信号选择正向偏置或反向偏置，并将所选择的偏压施加到步进恢复二极管; 正向电流源，其可操作以在将正向偏压施加到阶跃恢复二极管时规定要提供给阶跃恢复二极管的正向电流; 以及反向电流源，当反向偏置被施加到阶跃恢复二极管时，其可操作地规定要提供给阶跃恢复二极管的反向电流。

87. 发明授权

US5426682A Sequential logic circuit having state hold circuits 失效
标题翻译：具有状态保持电路的顺序逻辑电路
公开(公告)号：US5426682A
公开(公告)日：1995-06-20
申请号：US797936
申请日：1991-11-26
申请人： Motomu Takatsu
发明人： Motomu Takatsu
IPC分类号： G06F7/00 , G05B19/07 , G11C19/28 , H03K3/36 , H03K19/21 , H03K23/54 , G11C19/00
CPC分类号： H03K3/36 , G05B19/07 , H03K19/212
摘要： A sequential logic circuit includes N state hold circuit where N is an integer. Each of the state hold circuits has a first input terminal, a second input terminal and an output terminal. The state hold circuits are cascaded via the respective first input terminals. The second input terminals of the state hold circuits receive a first clock signal. The first input terminal of one of the state hold circuits in a first stage receives a data signal. The output signal is obtained via the output terminal of one of the state hold circuits in a final stage. Each of the state hold circuits has the following truth table:______________________________________ A B Qn + 1 ______________________________________ 0 0 1 or 0 0 1 Qn 1 0 Qn 1 1 0 or 1 ______________________________________ wherein A and B designate the respective logic level signals applied to the first and second input terminals and Qn+1 designates the respective logic level of the resultant, current output signal produced at the output terminal in response to the corresponding, current logic levels input signals A and B, Qn representing that the prior logic level output signal is maintained as the current logic level output signal.
摘要翻译：顺序逻辑电路包括N状态保持电路，其中N是整数。每个状态保持电路具有第一输入端，第二输入端和输出端。状态保持电路经由各自的第一输入端子级联。状态保持电路的第二输入端接收第一时钟信号。第一级的状态保持电路之一的第一输入端接收数据信号。输出信号通过最后一级状态保持电路之一的输出端获得。每个状态保持电路具有以下真值表：-AB Qn + 1 -0 0 1或0 -0 1 Qn -1 0 Qn -1 1 0或1 - 其中A和B表示施加到第一和第二输入端和Qn + 1表示响应于对应的当前逻辑电平输入信号A和B的输出端产生的所得到的当前输出信号的相应逻辑电平，Qn表示先前的逻辑电平输出信号保持为当前逻辑电平输出信号。

88. 发明授权

US5260609A Logic circuit uising transistor having negative differential conductance 失效
标题翻译：使用具有负微分电导的晶体管的逻辑电路
公开(公告)号：US5260609A
公开(公告)日：1993-11-09
申请号：US945591
申请日：1992-09-16
申请人： Motomu Takatsu
发明人： Motomu Takatsu
IPC分类号： H01L27/06 , H03K3/36 , H03K19/08 , H03K19/21 , H03K19/013 , H03K4/787
CPC分类号： H03K3/36 , H01L27/0605 , H03K19/08 , H03K19/212
摘要： A logic circuit first, second and third input terminals, an output terminal, a load resistance element, and a transistor having a negative differential conductance. The collector is connected to the output terminal and coupled to a first power source via the load resistance element. The emitter is connected to a second power source. First, second and third resistors are connected between the base of the transistor and the first, second and third input terminals, respectively. A fourth resistor is connected between the base and emitter of the transistor. The resistance values of the first, second, third and fourth resistors are selected so that the transistor has first and second operating points respectively obtained when all the first, second and third input terminals are at a low level and when two of the first, second and third input terminals are at a high level, and has third and fourth operating points respectively obtained when one of the first, second and third input terminals is at the high level and when all the first, second and third input terminals are at the high level. A collector current obtained at the first and second operating points is less than that obtained at the third and fourth operating points.
摘要翻译：逻辑电路第一，第二和第三输入端子，输出端子，负载电阻元件和具有负微分电导的晶体管。集电极连接到输出端并通过负载电阻元件耦合到第一电源。发射极连接到第二个电源。首先，第二和第三电阻分别连接在晶体管的基极与第一，第二和第三输入端之间。第四电阻连接在晶体管的基极和发射极之间。选择第一，第二，第三和第四电阻器的电阻值，使得晶体管具有在所有第一，第二和第三输入端子处于低电平时分别获得的第一和第二工作点，以及当第一，第二，第二电阻并且第三输入端子处于高电平，并且当第一，第二和第三输入端子之一处于高电平时，并且当所有第一，第二和第三输入端子处于高电平时，分别具有第三和第四工作点水平。在第一和第二操作点获得的集电极电流小于在第三和第四操作点获得的集电极电流。

89. 发明授权

US4788662A Semiconductor memory device using resonant-tunneling hot electron transistor 失效
标题翻译：使用谐振隧道热电子晶体管的半导体存储器件
公开(公告)号：US4788662A
公开(公告)日：1988-11-29
申请号：US061288
申请日：1987-06-12
申请人： Toshihiko Mori
发明人： Toshihiko Mori
IPC分类号： G11C11/411 , G11C11/34 , G11C11/36 , G11C11/39 , G11C11/41 , G11C11/56 , H01L27/10 , H01L29/201 , H01L29/68 , H03K3/357 , H03K3/36 , H03K23/00 , G11C11/40 , G11C13/00
CPC分类号： B82Y10/00 , G11C11/34 , G11C11/36 , G11C11/39 , G11C11/56 , H03K23/00 , H03K3/36 , G11C2211/5614
摘要： A semiconductor memory device comprises an address line, a write line, a read line, and a memory cell connected to the address, write and read lines, where the memory cell comprises a power source, an RHET, a switching element and a data transfer element. The power source is coupled to a base of the RHET through a first resistor so that the RHET has a plurality of stable states. The switching element is coupled between the write line and the base of the RHET, and is controlled by a signal from the address line. The data transfer element is coupled between a collector of the RHET and the read line, and the collector is coupled to the power source through a second resistor. When reading an information from the memory cell, a signal corresponding to one of the plurality of stable states of the RHET is transmitted to the read line via the data transfer element.
摘要翻译：半导体存储器件包括地址线，写入线，读取线和连接到地址，写入和读取线的存储单元，其中存储器单元包括电源，RHET，开关元件和数据传输元件。电源通过第一电阻器耦合到RHET的基极，使得RHET具有多个稳定状态。开关元件耦合在写入线和RHET的基极之间，并由来自地址线的信号控制。数据传输元件耦合在RHET的集电极和读取线之间，并且集电极通过第二电阻耦合到电源。当从存储单元读取信息时，与RHET的多个稳定状态之一相对应的信号经由数据传送元件发送到读取线。

90. 发明授权

US4463268A Varistors with controllable voltage versus time response and method for using the same to provide a rectangular voltage pulse 失效
标题翻译：具有可控电压对时间响应的压敏电阻器及其使用方法提供矩形电压脉冲
公开(公告)号：US4463268A
公开(公告)日：1984-07-31
申请号：US499609
申请日：1983-05-31
申请人： Lionel M. Levinson
发明人： Lionel M. Levinson
IPC分类号： H01C7/112 , H03K3/36
CPC分类号： H01C7/112
摘要： A bismuth-free, zinc oxide based varistor exhibits a controllable overshoot/undershoot voltage characteristic. The varistor is composed of zinc oxide as the primary constituent, with smaller quantities of barium, boron, one or more transition elements and aluminum. Varistor voltage versus time response is dependent on the degree of aluminum doping. Typically, more than approximately 0.003 mole percent, but less than approximately 0.1 mole percent aluminum is employed, depending on desired voltage overshoot/undershoot characteristic. Varistors having a controllable voltage versus time response are used in a method for providing a rectangular voltage pulse in response to a current input.
摘要翻译：无铋氧化锌基变阻器具有可控的过冲/下冲电压特性。变阻器由氧化锌作为主要成分，较少量的钡，硼，一种或多种过渡元素和铝构成。压敏电阻电压对时间响应取决于铝掺杂的程度。通常，取决于所需的电压过冲/下冲特性，使用大于约0.003摩尔％但小于约0.1摩尔％的铝。具有可控电压对时间响应的压敏电阻用于响应于电流输入提供矩形电压脉冲的方法。

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