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    • 1. 发明申请
    • STREAM ENCRYPTION METHOD AND ENCRYPTION SYSTEM
    • 流加密方法和加密系统
    • US20100008497A1
    • 2010-01-14
    • US12492841
    • 2009-06-26
    • Motomu TAKATSU
    • Motomu TAKATSU
    • H04L9/20
    • H04L9/0656H04L9/002
    • A stream encryption method encodes plaintext of N number of 1-bit input, signal sequences into L (L is N or more) bits of encrypted text using N number of pseudo random sequences and uses only one pseudo random sequence used for the encryption to decode the single corresponding plaintext. This stream encryption method comprises using the N number of pseudo random sequences to divide a L-bit encryption symbol set, averagely into two equal parts; selecting either of the two partial sets by a corresponding 1-bit plaintext sequence; and when there are one or more elements of the selected N number of partial sets forming common parts in the sets, using one of those as an encryption symbol.
    • 流加密方法使用N个伪随机序列将N个1比特输入的信号序列的明文输入L(L是N个或更多个)加密文本的比特,并且仅使用用于加密的一个伪随机序列进行解码 单一对应的明文。 该流加密方法包括使用N个伪随机序列将L比特加密符号集平均分成两部分; 通过相应的1位明文序列选择两个部分集合中的任一个; 并且当所选择的N个部分集合中的一个或多个元素在集合中形成公共部分时,使用其中的一个作为加密符号。
    • 4. 发明授权
    • Arithmetic unit, correlation arithmetic unit and dynamic image compression apparatus
    • 算术单元,相关运算单元和动态图像压缩装置
    • US06292586B1
    • 2001-09-18
    • US09236345
    • 1999-01-25
    • Susumu KawakamiHiroaki OkamotoMotomu Takatsu
    • Susumu KawakamiHiroaki OkamotoMotomu Takatsu
    • G06K936
    • G06F17/15
    • In a correlation arithmetic system adapted to detect a relative difference between two functions, an operation is simplified. This makes it possible to perform the operation with a small scale of hardware and also with great accuracy. There is adopted an operation g*h instead of the “product” in the correlation arithmetic operation. There is disclosed an arithmetic unit in which two numeral values a and b are inputted, and the two numerical values a and b are subjected to a predetermined operation process, so that a numerical value c representative of an operation result is derived. The arithmetic unit has an absolute value operation unit for evaluating an absolute value |c| of the numerical value c, and a sign operation unit for evaluating a sign “sing (c)” of the numerical value c.
    • 在适于检测两个功能之间的相对差异的相关运算系统中,简化了操作。 这使得可以以小规模的硬件并且以很高的精度执行操作。 在相关算术运算中采用运算g * h而不是“乘积”。 公开了一种运算单元,其中输入两个数字值a和b,并且对两个数值a和b进行预定的操作处理,从而导出代表运算结果的数值c。 算术单元具有用于评估绝对值| c |的绝对值运算单元 的数值c的符号“sing(c)”的符号运算单元。
    • 6. 发明授权
    • Majority logic circuit
    • 多数逻辑电路
    • US5281871A
    • 1994-01-25
    • US795472
    • 1991-11-21
    • Toshihiko MoriMotomu Takatsu
    • Toshihiko MoriMotomu Takatsu
    • G06F7/50G06F7/501H03K19/21H03K19/23H03K19/013
    • G06F7/5013H03K19/212H03K19/215H03K19/23G06F2207/4822
    • A logic circuit including a transistor having a control electrode connected to three input terminals at which are received three respective input signals, each having, selectively, either a high or a low voltage level, and first and second electrodes, one thereof connected to a first power supply potential and the other thereof connected through a diode having N-type negative differential resistance to a second, lower power supply potential. An output terminal is connected to one of the first and second electrodes of the transistor for deriving an output signal. The load lines of the transistor are set to a first operating point for both a first condition in which all three input signals are at a low voltage level and also a second condition in which two thereof are at a high level and the third is at a low level, and to a second operating point for both a third condition in which only one of the input signals is at the high level and the remaining two input signals are at the low level and also a fourth condition in which all of the three input signals are at the high level. The current conducted by the transistor is at a first level for the first operating point and at a second level, greater than the first level, for the second operating point.
    • 一种逻辑电路,包括具有连接到三个输入端子的控制电极的晶体管,在三个输入端子处接收三个相应的输入信号,每个输入信号选择性地具有高电压或低电压电平,以及第一和第二电极,其中一个连接到第一 电源电位,另一个通过具有N型负差分电阻的二极管连接到第二较低电源电位。 输出端子连接到晶体管的第一和第二电极之一,用于导出输出信号。 对于其中所有三个输入信号都处于低电压电平的第一状态以及其中两个处于高电平的第二状态,并且第三状态处于高电平的第二状态,晶体管的负载线被设置为第一工作点 低电平的第二工作点,对于其中只有一个输入信号处于高电平且剩余的两个输入信号处于低电平的第三状态,以及其中三个输入的全部的第四条件 信号处于高位。 对于第二工作点,由晶体管传导的电流为第一工作点的第一电平,大于第一电平的第二电平。
    • 7. 发明授权
    • Information recording and reproducing apparatus and method, and signal decoding circuit for performing timing recovery
    • 信息记录和再现装置和方法以及用于执行定时恢复的信号解码电路
    • US07515369B2
    • 2009-04-07
    • US11388377
    • 2006-03-24
    • Takao SugawaraMotomu TakatsuMasaru Sawada
    • Takao SugawaraMotomu TakatsuMasaru Sawada
    • G11B5/09
    • G11B20/10009G11B5/09G11B20/18
    • A timing recovery unit detects a phase offset and a frequency offset from a head area of reproduction data and initially corrects them. The timing recovery unit stores data in which a head reproduction signal has been made to be discrete by a fixed clock into a buffer. A phase offset detector detects the phase offset from the data head area in parallel with the operation for writing the data into the buffer. At the same time, a frequency offset detector detects the frequency offset from the data head area in parallel with the operation for writing the data into the buffer. A correction value of the detected phase offset and a correction value of the detected frequency offset are initially set into a digital PLL. While the data is read out from the buffer, a frequency lead-in and a phase lead-in are executed in the head area.
    • 定时恢复单元从再现数据的头部区域检测相位偏移和频率偏移,并且最初校正它们。 定时恢复单元将已经通过固定时钟将头重放信号离散的数据存储到缓冲器中。 相位偏移检测器与将数据写入缓冲器的操作并行地检测与数据头区域的相位偏移。 同时,频率偏移检测器与将数据写入缓冲器的操作并行地检测数据头区域的频率偏移。 检测到的相位偏移的校正值和检测到的频率偏移的校正值最初被设置为数字PLL。 当从缓冲器中读出数据时,在头部区域中执行频率导入和相位导入。
    • 9. 发明授权
    • Data processing circuit adapted for use in pattern matching
    • 适用于模式匹配的数据处理电路
    • US6032167A
    • 2000-02-29
    • US44973
    • 1998-03-20
    • Motomu Takatsu
    • Motomu Takatsu
    • G06T7/40G06F17/10G06T7/20G06T7/60G06F15/00
    • G06T7/206
    • A data processing circuit adapted for use in pattern matching between two sets of multi-dimensional signal data. The data processing circuit performs integration-based conversion on data aw calculated by multiplying first multi-dimensional signal data a by a window function w, second multi-dimensional signal data b, data b.sup.2 calculated by squaring the data b, and the window function w, calculates a correlation between the first and second multi-dimensional signal data items a and b on the basis of the data aw and data b subjected to integration-based conversion, calculates a means of deviations from the square of the second multi-dimensional signal data b on the basis of the data b.sup.2 and window function subjected to integration-based conversion, and calculates a portion of the second multi-dimensional signal data b most consistent with the first multi-dimensional signal data a multiplied by the window function w. Owing to this processing, a motion vector (magnitude of movement) can be detected by carrying out a small number of arithmetic operations while hardly being affected by the variation of a signal representing the multi-dimensional signal data used for comparison. This contributes to high-precision pattern matching.
    • 一种数据处理电路,适用于两组多维信号数据之间的模式匹配。 数据处理电路对通过将第一多维信号数据a乘以窗函数w,第二多维信号数据b,通过平方数据b计算出的数据b2和窗函数w来计算的数据aw执行基于积分的转换 基于经过基于积分的转换的数据aw和数据b计算第一和第二多维信号数据项a和b之间的相关性,计算与第二多维信号的平方的偏差的平均值 数据b基于经过基于积分的转换的数据b2和窗口函数,并且计算与第一多维信号数据a最相符的第二多维信号数据b的一部分乘以窗函数w。 由于这种处理,通过执行少量的算术运算,可以检测运动矢量(运动的大小),同时几乎不受表示用于比较的多维信号数据的信号的变化的影响。 这有助于高精度模式匹配。
    • 10. 发明授权
    • Sequential logic circuit having state hold circuits
    • 具有状态保持电路的顺序逻辑电路
    • US5426682A
    • 1995-06-20
    • US797936
    • 1991-11-26
    • Motomu Takatsu
    • Motomu Takatsu
    • G06F7/00G05B19/07G11C19/28H03K3/36H03K19/21H03K23/54G11C19/00
    • H03K3/36G05B19/07H03K19/212
    • A sequential logic circuit includes N state hold circuit where N is an integer. Each of the state hold circuits has a first input terminal, a second input terminal and an output terminal. The state hold circuits are cascaded via the respective first input terminals. The second input terminals of the state hold circuits receive a first clock signal. The first input terminal of one of the state hold circuits in a first stage receives a data signal. The output signal is obtained via the output terminal of one of the state hold circuits in a final stage. Each of the state hold circuits has the following truth table:______________________________________ A B Qn + 1 ______________________________________ 0 0 1 or 0 0 1 Qn 1 0 Qn 1 1 0 or 1 ______________________________________ wherein A and B designate the respective logic level signals applied to the first and second input terminals and Qn+1 designates the respective logic level of the resultant, current output signal produced at the output terminal in response to the corresponding, current logic levels input signals A and B, Qn representing that the prior logic level output signal is maintained as the current logic level output signal.
    • 顺序逻辑电路包括N状态保持电路,其中N是整数。 每个状态保持电路具有第一输入端,第二输入端和输出端。 状态保持电路经由各自的第一输入端子级联。 状态保持电路的第二输入端接收第一时钟信号。 第一级的状态保持电路之一的第一输入端接收数据信号。 输出信号通过最后一级状态保持电路之一的输出端获得。 每个状态保持电路具有以下真值表:-AB Qn + 1 -0 0 1或0 -0 1 Qn -1 0 Qn -1 1 0或1 - 其中A和B表示施加到 第一和第二输入端和Qn + 1表示响应于对应的当前逻辑电平输入信号A和B的输出端产生的所得到的当前输出信号的相应逻辑电平,Qn表示先前的逻辑电平输出 信号保持为当前逻辑电平输出信号。