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81. 发明申请

US20150117564A1 INDUCTOR-LESS 50% DUTY CYCLE WIDE-RANGE DIVIDE-BY-3 CIRCUIT 有权
标题翻译：电感器不足50％占空比宽范围分流三路电路
公开(公告)号：US20150117564A1
公开(公告)日：2015-04-30
申请号：US14064987
申请日：2013-10-28
申请人： QUALCOMM Incorporated
发明人： Ali SAJJADI , Babak VAKILI-AMINI
IPC分类号： H03K23/50 , H04L25/02
CPC分类号： H03K23/50 , H03K3/3562 , H03K21/10 , H03K23/544 , H04L25/02
摘要： Certain aspects of the present disclosure provide apparatus for producing an output signal having a duty cycle of 50% and a frequency that is one third that of an input signal. One example frequency dividing circuit for producing such an output signal generally includes first and second flip-flops; first, second, and third logic circuits, each configured to function equivalently to a logic OR gate; and an internal frequency dividing circuit configured to generate an output waveform having a frequency that is one half that of an input waveform.
摘要翻译：本公开的某些方面提供了用于产生占空比为50％，频率为输入信号的三分之一的输出信号的装置。用于产生这种输出信号的一个示例性分频电路通常包括第一和第二触发器; 第一，第二和第三逻辑电路，每个逻辑电路被配置为等效于逻辑或门功能; 以及内部分频电路，被配置为生成具有输入波形的一半的频率的输出波形。

82. 发明授权

US08237485B2 System and method for multiple-phase clock generation 有权
标题翻译：用于多相时钟生成的系统和方法
公开(公告)号：US08237485B2
公开(公告)日：2012-08-07
申请号：US12872371
申请日：2010-08-31
申请人： Hao Meng , Peiqi Xuan
发明人： Hao Meng , Peiqi Xuan
IPC分类号： G06F1/04
CPC分类号： G06F1/06 , H03K23/50
摘要： A system and method of clock generation to provide divided-by-2 clocks with prescribed phase shifts are disclosed. In a communication system with high-order harmonic mixing, the system requires LO signals with a set of prescribed phase shifts, such as 0°, 45°, 90°, and 135°, or 0°, 60° and 120°. Often, the clock generation system involves a divide-by-2 divider to derive the clock signals with the prescribed phase shifts. In a conventional implementation of the divide-by-2 divider, the system is subject to phase uncertainty in the output signal. Accordingly, a system comprises multiple latch pairs and respective differential clocks are used to generate the clocks with the set of correct prescribed phase shifts.
摘要翻译：公开了一种提供具有规定相移的二分之一秒钟的时钟产生系统和方法。在具有高次谐波混合的通信系统中，系统需要具有一定规定相移的LO信号，例如0°，45°，90°和135°，或0°，60°和120°。通常，时钟发生系统涉及一个除以2的分频器，以规定的相移导出时钟信号。在2分频器的传统实现中，系统在输出信号中受到相位不确定性的影响。因此，系统包括多个锁存器对，并且使用相应的差分时钟来产生具有正确规定相移集合的时钟。

83. 发明授权

US08030975B2 Method and apparatus for generating frequency divided signals 有权
标题翻译：用于产生分频信号的方法和装置
公开(公告)号：US08030975B2
公开(公告)日：2011-10-04
申请号：US12886305
申请日：2010-09-20
申请人： Mel Bazes
发明人： Mel Bazes
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00
CPC分类号： H03K5/1534 , H03K23/50
摘要： A frequency divider includes a first frequency divider stage coupled to a clock signal and operative to generate a first frequency divided signal. A second frequency divider stage is coupled to the clock signal and to the first frequency divider stage and is operative to generate a second frequency divided signal. A third frequency divider stage is coupled to the clock signal and to the second frequency divider stage and is configured to generate a third frequency divided signal using only i) the clock signal and ii) the second frequency divided signal so that any transition of the third frequency divided signal occurs at an edge of the clock signal at which the second frequency divided signal does not transition.
摘要翻译：分频器包括耦合到时钟信号并用于产生第一分频信号的第一分频器级。第二分频器级耦合到时钟信号和第一分频器级，并且可操作以产生第二分频信号。第三分频器级耦合到时钟信号和第二分频器级，并且被配置为仅使用i）时钟信号并且ii）第二分频信号来产生第三分频信号，使得第三分频器级的任何转换频率分频信号发生在第二分频信号不转变的时钟信号的边沿。

84. 发明申请

US20110006816A1 Method and Apparatus for Generating Frequency Divided Signals 有权
标题翻译：用于产生分频信号的方法和装置
公开(公告)号：US20110006816A1
公开(公告)日：2011-01-13
申请号：US12886305
申请日：2010-09-20
申请人： Mel Bazes
发明人： Mel Bazes
IPC分类号： H03B19/00
CPC分类号： H03K5/1534 , H03K23/50
摘要： In a method for dividing a frequency of a clock signal, a first frequency divided signal is generated based on a clock signal. Rising edges in the first frequency divided signal are detected. Alternatively, falling edges in the first frequency divided signal are detected. An edge detection signal that includes a pulse for each detected edge is generated. A second frequency divided signal is generated based on the edge detection signal.
摘要翻译：在分频时钟信号的频率的方法中，基于时钟信号产生第一分频信号。检测第一分频信号中的上升沿。或者，检测第一分频信号中的下降沿。生成包含每个检测边缘的脉冲的边缘检测信号。基于边缘检测信号产生第二分频信号。

85. 发明申请

US20070280403A1 Counter outputting count signal having random count value 审中-公开
标题翻译：计数器输出具有随机计数值的计数信号
公开(公告)号：US20070280403A1
公开(公告)日：2007-12-06
申请号：US11488839
申请日：2006-07-19
申请人： Byung Ryul Kim
发明人： Byung Ryul Kim
IPC分类号： H03K25/00
CPC分类号： H03K23/50
摘要： A counter that outputs a counting signal having a random counting value. The counter includes a clock generator and a counting circuit. The clock generator generates first and second clock signals with different phases based on an input clock signal. The counting circuit executes a counting operation and outputs a counting signal having a random counting value, in response to the first and second clock signals. The counter can output a counting signal having a random counting value. Accordingly, semiconductor devices to which the counter is applied can execute a variety of operations.
摘要翻译：输出具有随机计数值的计数信号的计数器。计数器包括时钟发生器和计数电路。时钟发生器基于输入时钟信号产生具有不同相位的第一和第二时钟信号。计数电路响应于第一和第二时钟信号执行计数操作并输出具有随机计数值的计数信号。计数器可以输出具有随机计数值的计数信号。因此，应用了计数器的半导体器件可以执行各种操作。

86. 发明授权

US07298811B2 Synchronous frequency dividers and components therefor 失效
标题翻译：同步分频器及其组件
公开(公告)号：US07298811B2
公开(公告)日：2007-11-20
申请号：US11343234
申请日：2006-01-31
申请人： Bardo Müller
发明人： Bardo Müller
IPC分类号： H03B19/00 , G06F7/68
CPC分类号： H03K23/50 , H03K3/2885 , H03K23/665
摘要： The invention discloses a frequency divider using half-adding functions, comprising one latch circuitry with half adding function for each digit, each latch circuitry receiving its output signal Sout at its S-input, the latch circuitry (76) for the least significant bit receiving at its Carry-input a “1”, and each further latch circuity receiving at its Carry-input the carry signal from the latch circuitry of the previous digit, and an And gate circuitry receiving the Sum outputs of the latch circuitries.
摘要翻译：本发明公开了一种使用半加法功能的分频器，包括一个具有每个数字加半功能的锁存电路，每个锁存电路在其S输入端接收其输出信号Sout，锁存电路（76）用于最低有效位接收在其进位输入处为“1”，并且每个进一步的锁存电路在其进位输入处接收来自前一个数字的锁存电路的进位信号，以及接收锁存电路的和输出的“和”门电路。

87. 发明授权

US07190756B1 Hybrid counter with an asynchronous front end 有权
标题翻译：具有异步前端的混合计数器
公开(公告)号：US07190756B1
公开(公告)日：2007-03-13
申请号：US10954889
申请日：2004-09-29
申请人： Alireza S. Kaviani , Carlos M. Vasquez
发明人： Alireza S. Kaviani , Carlos M. Vasquez
IPC分类号： H03K21/00 , H03K23/00
CPC分类号： H03K23/50 , H03K21/023
摘要： Integrated circuit counting apparatuses are described. More particularly, a hybrid counter (203) including an asynchronous counter (310) front end and a synchronous counter (311) back end is described. The asynchronous counter (310) including at least one asynchronous counter stage (341, 342, 343) having an asynchronous level-mode state machine (381, 382). The asynchronous level-mode state machine formed of Differential Cascode Voltage Switch Logic.
摘要翻译：对集成电路计数装置进行说明。更具体地，描述了包括异步计数器（310）前端和同步计数器（311）后端的混合计数器（203）。异步计数器（310）包括具有异步电平模式状态机（381,382）的至少一个异步计数器级（341,342,343）。由差分串联电压开关逻辑组成的异步电平状态机。

88. 发明申请

US20070046340A1 CLOCK FREQUENCY DIVIDER CIRCUIT AND METHOD OF DIVIDING CLOCK FREQUENCY 有权
标题翻译：时钟频率分频电路及分频时钟分频方法
公开(公告)号：US20070046340A1
公开(公告)日：2007-03-01
申请号：US11162160
申请日：2005-08-31
申请人： Min-Chung Chou , Shu-Fang Wu
发明人： Min-Chung Chou , Shu-Fang Wu
IPC分类号： H03K23/00
CPC分类号： H03K23/50
摘要： A clock frequency divider circuit and method of dividing a clock frequency are provided. The clock frequency divider circuit includes a first flip-flop circuit, a second flip-flop circuit, a third flip-flop circuit, a first logic control unit and a second logic control unit, wherein the first flip-flop circuit has two clock input terminals connected to the second and third flip-flop circuits respectively and two control signal input terminals connected to the first and second logic control units respectively. The second and third flip-flop circuits count rising edges and falling edges of an input frequency under control of the first and second flip-flop circuits and accordingly, symmetric output signals are output from the first flip-flop circuit.
摘要翻译：提供时钟分频器电路和分频时钟频率的方法。时钟分频器电路包括第一触发器电路，第二触发器电路，第三触发器电路，第一逻辑控制单元和第二逻辑控制单元，其中第一触发器电路具有两个时钟输入分别连接到第二和第三触发器电路的端子和分别连接到第一和第二逻辑控制单元的两个控制信号输入端子。第二和第三触发器电路在第一和第二触发器电路的控制下对输入频率的上升沿和下降沿进行计数，因此从第一触发器电路输出对称的输出信号。

89. 发明授权

US07046052B1 Phase matched clock divider 有权
标题翻译：相位匹配时钟分频器
公开(公告)号：US07046052B1
公开(公告)日：2006-05-16
申请号：US10837210
申请日：2004-04-30
申请人： Andrew K. Percey , Raymond C. Pang
发明人： Andrew K. Percey , Raymond C. Pang
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00
CPC分类号： H03K23/50
摘要： A phase matched clock divider includes a first feed-through flip-flop that receives a first input clock signal, and in response, provides a first output clock signal having the same frequency. The first feed-through flip-flop is enabled and disabled in response to a first reset signal. A plurality of series-connected flip-flops each receives the first input clock signal, and in response, provides a divided output clock signal. Each of the series-connected flip-flops is enabled and disabled in response to a second reset signal. The first and second release signals asynchronously disable the associated flip-flops in response to a third reset signal. The first release signal synchronously enables the first feed-through flip-flop in response to the third reset signal and a release clock signal. The second release signal enables the series-connected flip-flops in response to the third reset signal and a release control signal.
摘要翻译：相位匹配时钟分频器包括接收第一输入时钟信号的第一馈通触发器，并且作为响应，提供具有相同频率的第一输出时钟信号。响应于第一复位信号，第一馈通触发器被使能和禁止。多个串联触发器各自接收第一输入时钟信号，作为响应，提供分频的输出时钟信号。每个串联的触发器响应于第二复位信号被使能和禁止。响应于第三复位信号，第一和第二释放信号异步地禁用相关联的触发器。响应于第三复位信号和释放时钟信号，第一释放信号同步使第一馈通触发器使能。第二释放信号使得串联连接的触发器响应于第三复位信号和释放控制信号。

90. 发明授权

US06937688B2 State machine, counter and related method for gating redundant triggering clocks according to initial state 有权
标题翻译：根据初始状态选通冗余触发时钟的状态机，计数器和相关方法
公开(公告)号：US06937688B2
公开(公告)日：2005-08-30
申请号：US10065967
申请日：2002-12-05
申请人： Yung-Huei Chen , Shan-Ting Hong
发明人： Yung-Huei Chen , Shan-Ting Hong
IPC分类号： H03K21/00 , H03K21/16 , H03K23/50 , H03K23/66 , H03K25/00
CPC分类号： H03K23/667 , H03K21/00 , H03K23/50
摘要： A state machine, a counter, and related method for gating redundant triggering clocks according to the initial states is provided. The state machine includes a plurality of state units and a clock gating circuit. Each of the state unit is triggered by a clock to generate a corresponding varying state, and the clock gating circuit is capable of selectively withholding a triggering clock to at least one state unit according only to an initial state, such that the selected state unit(s) will not be triggered by the triggering clock while the rest of the state units are triggered by the triggering clock to update their corresponding states.
摘要翻译：提供了根据初始状态选通冗余触发时钟的状态机，计数器和相关方法。状态机包括多个状态单元和时钟门控电路。每个状态单元由时钟触发以产生相应的变化状态，并且时钟门控电路能够根据初始状态选择性地将触发时钟保留到至少一个状态单元，使得所选状态单元 s）不会被触发时钟触发，而其余状态单元由触发时钟触发以更新其相应状态。

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