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81. 发明授权

US06233675B1 Facility to allow fast execution of and, or, and test instructions 失效
标题翻译：允许快速执行和/或测试指令的设施
公开(公告)号：US06233675B1
公开(公告)日：2001-05-15
申请号：US09276315
申请日：1999-03-25
申请人： Kenneth K. Munson , Peter C. Mills
发明人： Kenneth K. Munson , Peter C. Mills
IPC分类号： G06F9305
CPC分类号： G06F9/30029 , G06F9/30094 , G06F9/3867
摘要： Improvements are made in how microprocessors execute AND, OR, and TEST instructions when the operands of this instruction are equal. AND/OR/TEST instructions with equal operands are used to set flags based on the contents of the single operand without explicitly performing the actual AND/OR/TEST command. By resetting these flags directly, this mechanism allows these instructions to be paired with preceding dependent instructions simply by using the flags set by the AND/OR/TEST for the previous instruction. An architecture that hardwires the implementation into the microprocessor through logic gates is preferred. This will result in increased speed while reducing power consumption. Further, a full-sized ALU is not needed in order to execute the AND/OR/TEST instruction with equal operands. As this is a more direct procedure, a pipeline with a reduced capability ALU can be utilized.
摘要翻译：当本指令的操作数相等时，微处理器如何执行AND，OR或TEST指令。具有相等操作数的AND / OR / TEST指令用于基于单个操作数的内容设置标志，而不显式执行实际的AND / OR / TEST命令。通过直接复位这些标志，该机制可以简单地通过使用由AND / OR / TEST为先前指令设置的标志，将这些指令与先前的相关指令进行配对。通过逻辑门硬实现微处理器的架构是优选的。这将导致速度提高，同时降低功耗。此外，为了以相同的操作数执行AND / OR / TEST指令，不需要全尺寸的ALU。由于这是一个更直接的过程，因此可以利用ALU能力降低的管道。

82. 发明授权

US6065028A Multifunctional macro 失效
标题翻译：多功能宏
公开(公告)号：US6065028A
公开(公告)日：2000-05-16
申请号：US716818
申请日：1996-09-16
申请人： Sang Hoo Dhong , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Joel Abraham Silberman
IPC分类号： G06F9/302 , G06F9/305 , G06F9/315 , G06F7/38
CPC分类号： G06F9/3001 , G06F9/30029 , G06F9/30032
摘要： Fixed point instructions ADD, ROTATE, COMPARE-TO-ZERO, AND, OR and COUNT-LEADING-ZEROS are each performable in one circuit or macro. Such fixed point instructions may be implemented within an execution unit in a microprocessor, microcontroller, or digital signal processor.
摘要翻译：固定点指令ADD，ROTATE，COMPARE-TO-ZERO，AND，OR和COUNT-LEADING-ZEROS都可以在一个电路或宏中执行。这样的固定点指令可以在微处理器，微控制器或数字信号处理器的执行单元内实现。

83. 发明授权

US6055623A Specialized millicode instruction for editing functions 失效
标题翻译：专用的millicode指令用于编辑功能
公开(公告)号：US6055623A
公开(公告)日：2000-04-25
申请号：US56344
申请日：1998-04-07
申请人： Charles Franklin Webb , Judy Shan-Shan Chen Johnson
发明人： Charles Franklin Webb , Judy Shan-Shan Chen Johnson
IPC分类号： G06F9/38 , G06F9/22 , G06F9/28 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/308 , G06F9/318 , G06F9/32
CPC分类号： G06F9/3822 , G06F9/3001 , G06F9/30018 , G06F9/30029 , G06F9/30094 , G06F9/30145 , G06F9/3017 , G06F9/30181
摘要： A computer system having a pipelined computer processor, which executes a relatively simple instruction set in a hardware controlled execution unit and executes a relatively complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in said hardware controlled execution unit, a millicode operating in a milli-mode state when macro-mode decoding by said processor is suspended to cause the system to subsequently use processor milli-registers and the processor's decoder decodes them and schedules them for execution upon entry into the processor milli-mode. Millicode flags allow specialized update and branch instructions and flags are either cleared or specifically set for a millicode instruction. A millicode instruction for editing functions processes one byte of an input pattern string, generates one byte of an output string, and updates various pointers and state indications to prepare for processing the next byte in a string. Translate Fetch (TRFET) millicode instructions support a Translate and Test TRT instruction and specialized millicode instructions for packed decimal division make use of the hardware control and dataflow logic designed to support simpler packed decimal operations including Add to provide operand access, checking, preparation, and storing functions, and to generate the quotient digits as needed for the DP instruction are implemented as as internal code instructions, rather than implementing the entire DP function in hardware, and control is maintained in internal code allowing simpler handling of unusual and boundary conditions.
摘要翻译：一种具有流水线计算机处理器的计算机系统，其在硬件控制执行单元中执行相对简单的指令集，并且在所述硬件控制的执行单元中以简单指令的毫位序列在毫模式架构状态下执行相对复杂的指令集，当所述处理器的宏模式解码被暂停以使得系统随后使用处理器毫秒寄存器并且处理器的解码器对它们进行解码并在进入处理器毫模式时进行调度以进行执行，则以毫模式状态工作的微代码。 Millicode标志允许专门的更新和分支指令和标志被清除或专门设置为一个millicode指令。用于编辑功能的millicode指令处理输入模式字符串的一个字节，生成输出字符串的一个字节，并更新各种指针和状态指示，以准备处理字符串中的下一个字节。 Translate Fetch（TRFET）millicode指令支持翻译和测试TRT指令和专门的millicode指令，用于打包十进制分割，使用硬件控制和数据流逻辑，用于支持更简单的打包十进制操作，包括添加以提供操作数访问，检查，准备和存储功能，并根据DP指令的需要生成商数字，作为内部代码指令而实现，而不是在硬件中实现整个DP功能，并且内部代码中的控制保持在更简单的处理异常和边界条件中。

84. 发明授权

US6023759A System for observing internal processor events utilizing a pipeline data path to pipeline internally generated signals representative of the event 失效
标题翻译：用于利用流水线数据路径观察内部处理器事件的系统，用于管理表示事件的内部产生的信号
公开(公告)号：US6023759A
公开(公告)日：2000-02-08
申请号：US940733
申请日：1997-09-30
申请人： E. Theodore L. Omtzigt
发明人： E. Theodore L. Omtzigt
IPC分类号： G06F9/30 , G06F9/305 , G06F9/38 , G06F11/34 , G06F11/28
CPC分类号： G06F9/30032 , G06F11/3466 , G06F9/30003 , G06F9/30029 , G06F9/3867 , G06F2201/86
摘要： The present invention discloses a method and system for observing and measuring in real-time an event inside a processor via an observation architecture (OA). The method comprises the steps of: (1) receiving a command instruction; the command instruction includes at least an opcode and an operand specifier; (2) decoding the command instruction by converting the opcode into control bits; (3) mapping the operand specifier to select at least one resource element of the observation architecture; and (4) capturing the event according to the control bits.
摘要翻译：本发明公开了一种通过观察架构（OA）实时地观察和测量处理器内的事件的方法和系统。该方法包括以下步骤：（1）接收命令指令; 命令指令至少包括操作码和操作数说明符; （2）通过将操作码转换为控制位来解码命令指令; （3）映射操作数说明符以选择观测结构的至少一个资源元素; 和（4）根据控制位捕获事件。

85. 发明授权

US5884069A Computer and a method of operating a computer to combine data values within a singularly addressable data string 失效
标题翻译：计算机和操作计算机以将数据值组合在单个可寻址数据串中的方法
公开(公告)号：US5884069A
公开(公告)日：1999-03-16
申请号：US661077
申请日：1996-06-10
申请人： Nathan M. Sidwell
发明人： Nathan M. Sidwell
IPC分类号： G06F7/57 , G06F9/302 , G06F9/305 , G06F15/78
CPC分类号： G06F7/57 , G06F15/8076 , G06F9/30014 , G06F9/30029 , G06F9/30036 , G06F2207/382
摘要： There is disclosed a computer and a method of operating a computer to allow combination of data values in the context of the execution of so-called "packed instructions". A data string comprising a certain number of sub-strings representing discrete data values and which are not independently addressable is held in a source register store. A combining instruction which operates to carry out a polyadic operation on at least some of the sub-strings to generate a result sub-string is then executed.A result data string comprising said result sub-string is loaded into a destination register. These "combining" instructions have the advantage that they are general purpose instructions which can be used in a plurality of different situations. The instructions are particularly useful in a packed arithmetic environment.
摘要翻译：公开了一种计算机和操作计算机以允许在执行所谓的“打包指令”的上下文中组合数据值的方法。包括表示离散数据值并且不能独立寻址的一定数量的子串的数据串被保存在源寄存器存储器中。然后执行对至少一些子串执行多项式操作以产生结果子串的组合指令。包括所述结果子串的结果数据串被加载到目的地寄存器中。这些“组合”指令的优点在于它们是可以在多种不同情况下使用的通用指令。指令在打包运算环境中特别有用。

86. 发明授权

US5838986A RISC microprocessor architecture implementing multiple typed register sets 失效
公开(公告)号：US5838986A
公开(公告)日：1998-11-17
申请号：US937361
申请日：1997-09-25
申请人： Sanjiv Garg , Derek J. Lentz , Le Trong Nguyen , Sho Long Chen
发明人： Sanjiv Garg , Derek J. Lentz , Le Trong Nguyen , Sho Long Chen
IPC分类号： G06F9/30 , G06F9/305 , G06F9/318 , G06F9/34 , G06F9/38 , G06F9/42 , G06F9/46 , G06F9/48
CPC分类号： G06F9/30029 , G06F9/30036 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30138 , G06F9/30167 , G06F9/30181 , G06F9/3851
摘要： A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA�23:0!) and second (RA�31:24!) subsets, and a shadow subset (RT�31:24!). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively. Boolean comparison instructions specify particular integer or floating point registers for source data to be compared, and specify a particular Boolean register for the result, so there are no dedicated, fixed-location status flags. Boolean combinational instructions combine specified Boolean registers, for performing complex Boolean comparisons without intervening conditional branch instructions, to minimize pipeline disruption.

87. 发明授权

US5764939A RISC processor having coprocessor for executing circular mask instruction 失效
标题翻译：具有用于执行圆形掩码指令的协处理器的RISC处理器
公开(公告)号：US5764939A
公开(公告)日：1998-06-09
申请号：US540350
申请日：1995-10-06
申请人： Robert L. Caulk, Jr.
发明人： Robert L. Caulk, Jr.
IPC分类号： G06F9/302 , G06F9/305 , G06F9/38
CPC分类号： G06F9/3001 , G06F9/30029 , G06F9/30167 , G06F9/3885
摘要： An add with circular mask operation is executed in a RISC processor which includes a coprocessor having a register for storing a circular mask value. A circular mask instruction to the coprocessor includes a value in an immediate field and identifies a general register (RS), and a destination register (RT). The coprocessor operates on the value stored in the general register with the value in the immediate field and then masks the results using the circular mask value. The results are then stored in the destination register. The operation includes sign-extending the immediate field before adding to the contents of the general register to provide a sum, and the sum is then masked with the circular mask value.
摘要翻译：在包括具有用于存储圆形掩模值的寄存器的协处理器的RISC处理器中执行具有循环掩码操作的添加。向协处理器的圆形掩码指令包括立即字段中的值，并标识通用寄存器（RS）和目标寄存器（RT）。协处理器使用通用寄存器中存储的值与立即数字段中的值进行操作，然后使用圆形掩码值对结果进行掩码。然后将结果存储在目标寄存器中。该操作包括在添加到通用寄存器的内容之前对立即字段进行符号扩展以提供和，然后将该和被掩码为圆形掩码值。

88. 发明授权

US5734880A Hardware branching employing loop control registers loaded according to status of sections of an arithmetic logic unit divided into a plurality of sections 失效
标题翻译：硬件分支采用根据划分成多个部分的算术逻辑单元的部分的状态加载的循环控制寄存器
公开(公告)号：US5734880A
公开(公告)日：1998-03-31
申请号：US480230
申请日：1995-06-07
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/305 , G06F9/308 , G06F9/315 , G06F9/32 , G06F12/02 , G06F15/00
CPC分类号： G06F9/30014 , G06F12/0284 , G06F5/015 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30167 , G06F9/325
摘要： Conditional hardware branching employs zero overhead loop logic and writing to a loop count register within a program loop. The zero overhead loop logic includes a program counter (701), loop end registers (711, 712, 713), loop start registers (721, 722, 723), loop counter registers (731, 732, 733), comparators (715, 716, 717) and loop priority logic (725). Normally the program counter (701) is incremented each cycle. The comparators (715, 716, 717) compare the address stored in the program counter (701) with respective loop end registers (711, 712, 713). If the address in the program counter (701) equals a loop end address, loop priority logic (725) decrements the loop count register and loads the program counter with the loop start address in loop start register. Hardware looping involves loading a loop count register during program loop operation. An arithmetic logic unit operation generates a status bit loaded into a status register or is split into sections and generates a status bit for each section stored in a multiple flags register (211) used to load the loop. count register. If this is zero then the loop priority logic reloads the program counter (701) with the loop start address and repeats the loop. If this is nonzero, program counter (701) may increment normally or will be loaded with the loop start address of a higher priority loop.
摘要翻译：条件硬件分支采用零开销循环逻辑并写入程序循环内的循环计数寄存器。零开销循环逻辑包括程序计数器（701），循环结束寄存器（711,712,713），循环开始寄存器（721,722,723），循环计数器寄存器（731,732,733），比较器（715， 716,717）和循环优先级逻辑（725）。通常，每个周期递增程序计数器（701）。比较器（715,716,717）将存储在程序计数器（701）中的地址与相应的循环结束寄存器（711,712,713）进行比较。如果程序计数器（701）中的地址等于循环结束地址，则循环优先级逻辑（725）递减循环计数寄存器，并加载循环起始寄存器中循环起始地址的程序计数器。硬件循环涉及在程序循环操作期间加载循环计数寄存器。算术逻辑单元操作产生加载到状态寄存器中的状态位或分割成部分，并且生成用于加载循环的多标志寄存器（211）中存储的每个部分的状态位。计数寄存器如果这是零，则循环优先级逻辑使用循环起始地址重新加载程序计数器（701）并重复循环。如果这是非零的，则程序计数器（701）可以正常地增加或将加载较高优先级循环的循环起始地址。

89. 发明授权

US5694587A Specialized millicode instructions for test PSW validity, load with access test, and character translation assist 失效
标题翻译：测试PSW有效性的专用millicode指令，访问测试负载和字符翻译辅助
公开(公告)号：US5694587A
公开(公告)日：1997-12-02
申请号：US414154
申请日：1995-03-31
申请人： Charles Franklin Webb , Mark Steven Farrell , Mark Anthony Check , John Stephen Liptay
发明人： Charles Franklin Webb , Mark Steven Farrell , Mark Anthony Check , John Stephen Liptay
IPC分类号： G06F9/30 , G06F9/305 , G06F9/318 , G06F9/38 , G06F11/07
CPC分类号： G06F9/3865 , G06F11/0721 , G06F11/0751 , G06F9/30029 , G06F9/30087 , G06F9/30145 , G06F9/3017 , G06F9/30189
摘要： A pipelined computer processor in a milli-mode architected state tests the validity of a program status word with a mask stored in a millicode general register. The mask indicates bits in the program status word which are to be zeros if the word is valid. A logical AND operation is performed between correspondingly positioned bits in the word and bits in the mask and in addition the status of at least one other bit in the word is checked, a bit other than a correspondingly positioned bit.
摘要翻译：在毫模式架构状态下的流水线计算机处理器使用存储在毫通通用寄存器中的掩码测试程序状态字的有效性。掩码表示程序状态字中的位，如果该字有效，则它们将为零。在字中的相应位置的位和掩码中的位之间执行逻辑“与”运算，另外检查字中的至少一个其他位的状态，除了对应定位的位之外的位。

90. 发明授权

US5553309A Device for high speed evaluation of logical expressions and high speed vector operations 失效
标题翻译：用于高速评估逻辑表达式和高速矢量运算的装置
公开(公告)号：US5553309A
公开(公告)日：1996-09-03
申请号：US465902
申请日：1995-06-06
申请人： Kiyoshi Asai , Takeshi Nishikawa , Yoshiki Seo
发明人： Kiyoshi Asai , Takeshi Nishikawa , Yoshiki Seo
IPC分类号： G06F9/305 , G06F15/78 , G06F9/308 , G06F9/315
CPC分类号： G06F9/30029 , G06F15/8084
摘要： A logical expression operation device is embodied in hardware and is provided with an evaluation value operation means to operate logical expressions in vector data format and an evaluation value holding means to hold the operation result as intermediate evaluation values, and a control means which sequentially reads out the components of the logical expressions, judges the type of read component and controls the applicable means based on the judgment result and the status of the means to execute evaluation of said logical expressions with omitting the operation by the evaluation value operation means for a part in the logical expression corresponding to the secondary operated data of a particular operator. A vector operation device is provided with a data selecting means which reads out one of the vector data held at an input vector register and one of the data held at a mask register at a time and outputs the data as the first output data if the data from the mask register has a logical value "1" and as the second output data if the data from said mask register has a logical value "0". It is also provided with a first compress circuit which sequentially stores the first output data to the first output vector register and a second compress circuit which sequentially stores the second output data from said data selecting means to the second output vector register.
摘要翻译：逻辑表达式操作装置以硬件方式实现，并且具有评估值操作装置，用于操作向量数据格式的逻辑表达式和评估值保持装置，以将操作结果保持为中间评估值;以及控制装置，其依次读出逻辑表达式的组成部分判断读取组件的类型，并且基于判断结果和执行评估所述逻辑表达式的装置的状态来控制适用手段，而省略由评估值操作装置进行的操作的部分对应于特定操作员的辅助操作数据的逻辑表达式。向量操作装置设置有数据选择装置，其读取保持在输入向量寄存器处的矢量数据中的一个，并且一次保持在屏蔽寄存器中的数据之一，并且如果数据是数据，则输出该数据作为第一输出数据来自掩模寄存器的逻辑值为“1”，如果来自所述掩码寄存器的数据具有逻辑值“0”，则作为第二输出数据。还设置有第一压缩电路，其顺序地将第一输出数据存储到第一输出向量寄存器，以及第二压缩电路，其将来自所述数据选择装置的第二输出数据顺序地存储到第二输出向量寄存器。

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