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81. 发明授权

US4975868A Floating-point processor having pre-adjusted exponent bias for multiplication and division 失效
标题翻译：浮点处理器具有用于乘法和除法的预调整指数偏差
公开(公告)号：US4975868A
公开(公告)日：1990-12-04
申请号：US339279
申请日：1989-04-17
申请人： Donald L. Freerksen
发明人： Donald L. Freerksen
IPC分类号： G06F7/487 , G06F7/506 , G06F7/52 , G06F7/535 , G06F7/537
CPC分类号： G06F7/4876 , G06F7/535 , G06F7/5375 , G06F7/4873 , G06F7/4991 , G06F7/49936 , G06F7/49947
摘要： A floating-point arithmetic unit includes an exponent unit for biased exponents. Combinatorial bias-adjust logic removes the bias from one operand exponent before the two operand exponents are added together in adder for a multiply operation, and inserts a bias into one exponent before the exponents are subtracted by the adder for a divide operation.

82. 发明授权

US4943940A Floating point add/subtract and multiplying assemblies sharing common normalization, rounding and exponential apparatus 失效
标题翻译：浮点加法/乘法与共享共同的归一化，舍入和指数的装置
公开(公告)号：US4943940A
公开(公告)日：1990-07-24
申请号：US655482
申请日：1984-09-27
申请人： Bernard J. New
发明人： Bernard J. New
IPC分类号： G06F7/38 , G06F7/00 , G06F7/485 , G06F7/487 , G06F7/493 , G06F7/53 , G06F7/57 , G06F7/76
CPC分类号： G06F7/483 , G06F7/49905 , G06F7/49936 , G06F7/49947
摘要： A fully combinatorial floating point arithmetic apparatus is provided comprising separate fully combinatorial add/subtract and multiply assemblies which share a common normalization, rounding and exponential processing apparatus.
摘要翻译：提供了一种完全组合的浮点运算装置，其包括共享共同的归一化，舍入和指数处理装置的分离的完全组合的加/减和乘法组件。

83. 发明授权

US4896286A Floating-point arithmetic apparatus 失效
标题翻译：浮点算术装置
公开(公告)号：US4896286A
公开(公告)日：1990-01-23
申请号：US137924
申请日：1987-12-28
申请人： Katsuhiko Ueda
发明人： Katsuhiko Ueda
IPC分类号： G06F7/00 , G06F7/38 , G06F7/485 , G06F7/50 , G06F7/76
CPC分类号： G06F7/485 , G06F7/49936 , G06F7/49957
摘要： A floating-point arithmetic apparatus includes a first device for matching scales of first and second floating-point data. A second device serves to perform addition and subtraction between outputs from the first device. A third device serves to normalize output from the addition/subtraction device. A fourth device serves to round off output from the third device. A fifth device serves to calculate an absolute value of output from the third device. The fourth device and the fifth device may include a common adder.

84. 发明授权

US4849923A Apparatus and method for execution of floating point operations 失效
标题翻译：用于执行浮点运算的装置和方法
公开(公告)号：US4849923A
公开(公告)日：1989-07-18
申请号：US879337
申请日：1986-06-27
申请人： Sridhar Samudrala , Victor Peng , Nachum M. Gavrielov
发明人： Sridhar Samudrala , Victor Peng , Nachum M. Gavrielov
IPC分类号： G06F7/57
CPC分类号： G06F7/483 , G06F7/49915 , G06F7/49936 , G06F7/49947
摘要： In a floating point arithmetic execution unit, an additional adder unit and a selection network are added to the apparatus typically performing the arithmetic floating point function. The additional apparatus permits certain processes forming part of arithmetic operations to be executed in parallel. For selected arithmetic operations, the final result can be one of two values typically related by an intermediate shifting operation. By performing the processes in parallel and selecting the appropriate result, the execution time can be reduced when compared to the execution of the process in a serial implementation. The fundamental arithmetic operations of addition, subtraction, multiplication and division can each have the execution time decreased using the disclosed additional apparatus.
摘要翻译：在浮点算术执行单元中，附加加法器单元和选择网络被添加到通常执行算术浮点函数的装置中。附加装置允许并行执行形成算术运算的一部分的某些过程。对于所选的算术运算，最终结果可以是通常与中间移位操作相关的两个值之一。通过并行执行处理并选择适当的结果，与串行实现中的处理的执行相比，可以减少执行时间。使用所公开的附加装置，加法，减法，乘法和除法的基本算术运算各自可以使执行时间减少。

85. 发明授权

US4841467A Architecture to implement floating point multiply/accumulate operations 失效
标题翻译：架构实现浮点乘法/累加运算
公开(公告)号：US4841467A
公开(公告)日：1989-06-20
申请号：US104453
申请日：1987-10-05
申请人： Chung-Yih Ho , Karl J. Molnar , Daniel A. Staver
发明人： Chung-Yih Ho , Karl J. Molnar , Daniel A. Staver
IPC分类号： G06F7/485 , G06F7/50 , G06F7/544
CPC分类号： G06F7/485 , G06F7/5443 , G06F2207/3884 , G06F7/49936
摘要： A multiply/accumulator chip architecture capable of operating at a 20 megahertz system clock rate is designed so as to accept floating point numbers in sign magnitude form, to compute a product of the fractional portions thereof and to convert the fractional result into two's complement form for accumulation with the results of a previous product. This architecture readily permits the computation of vector-type inner product operations in a high speed pipelined fashion. Additionally, leading zero's and leadings one's detection is carried out in a multiply parallel fashion so as to rapidly produce post normalization results from the additive portion of the system. The system is implementable on a single integrated circuit chip in which an array multiplier is present so as to minimize inter-chip delays. The architecture of the present invention provides a high speed floating point multiply and accumulate operation with a short pipeline latency.
摘要翻译：设计能够以20兆赫系统时钟速率运行的乘法/累加器芯片架构，以便以符号幅度形式接受浮点数，计算其分数部分的乘积，并将分数结果转换成二进制补码形式，以便积累与以前的产品的结果。该架构容易地以高速流水线方式计算向量式内积运算。另外，领先的零和领先的检测是以并行的方式进行的，以便从系统的添加部分快速产生后归一化结果。该系统可以在单个集成电路芯片上实现，其中存在阵列乘法器以便最小化芯片间延迟。本发明的架构提供了一种具有短流水线延迟的高速浮点乘法和累加运算。

86. 发明授权

US4796218A Arithmetic circuit capable of executing floating point operation and fixed point operation 失效
标题翻译：能够执行浮点运算和定点运算的算术电路
公开(公告)号：US4796218A
公开(公告)日：1989-01-03
申请号：US16036
申请日：1987-02-18
申请人： Hideo Tanaka , Takao Nishitani
发明人： Hideo Tanaka , Takao Nishitani
IPC分类号： G06F7/38 , G06F7/487 , G06F7/508 , G06F7/57
CPC分类号： G06F7/483 , G06F7/49936
摘要： An arithmetic circuit comprises a pair of input registers for holding a pair of given numbers, and a radix point adjustment circuit coupled to the input registers for aligning the radix points of the given numbers. This adjsutment circuit is capable of outputting at least a pair of radix point aligned fractions and one exponent derived from the radix point alignment. An arithmetic operation circuit receives the pair of the radix point aligned fractions, and outputs the result of a given arithmetic operation of the received fractions and generates an overflow signal when an overflow is generated in the arithmetic operation of the received fractions. An exponent correction circuit receives the exponent from the adjustment circuit, and is responsive to the overflow signal from the arithmetic operation circuit so as to selectively correct the received exponent. A fraction correction circuit receives the output of the arithmetic operation circuit so as to correct the received data. There is provided a first selector receiving the output of the exponent correction circuit and responsive to a given control signal so as to selectively output the output of the exponent correction circuit or a predetermined value. Further, a second selector is provided to receive the outputs of the arithmetic operation circuit and the fraction correction circuit so as to selectively output one of the two received fractions in response to the control signal.
摘要翻译：运算电路包括一对用于保持一对给定数字的输入寄存器，以及耦合到输入寄存器的基数点调整电路，用于对准给定数字的小数点。该调整电路能够输出至少一对小数点对齐分数和从小数点对齐导出的一个指数。算术运算电路接收一对基点对齐分数，并输出接收分数的给定算术运算结果，并在接收分数的算术运算中产生溢出时产生溢出信号。指数校正电路从调整电路接收指数，并响应于来自算术运算电路的溢出信号，以选择性地校正接收指数。分数校正电路接收算术运算电路的输出，以校正接收到的数据。提供了接收指数校正电路的输出并响应于给定控制信号的第一选择器，以选择性地输出指数校正电路的输出或预定值。此外，提供第二选择器以接收算术运算电路和分数校正电路的输出，以便响应于控制信号选择性地输出两个接收分数中的一个。

87. 发明授权

US4295203A Automatic rounding of floating point operands 失效
标题翻译：自动舍入浮点运算符
公开(公告)号：US4295203A
公开(公告)日：1981-10-13
申请号：US92907
申请日：1979-11-09
申请人： Thomas F. Joyce
发明人： Thomas F. Joyce
IPC分类号： G06F7/57 , G06F7/48
CPC分类号： G06F7/483 , G06F7/49936 , G06F7/49947
摘要： If the firmware calls for an operand rounding operation, apparatus in the Scientific Instruction Processor (SIP) tests the bit to the right of the low order bit of the normalized operand to determine if a rounding cycle is required. If the operand requires a normalization cycle or a mantissa overflow correction cycle, the rounding operation is performed in those cycles.
摘要翻译：如果固件要求操作数舍入操作，则科学指令处理器（SIP）中的设备将测试归一化操作数的低位位右侧的位，以确定是否需要舍入周期。如果操作数需要归一化周期或尾数溢出校正周期，则在这些周期中执行舍入操作。

88. 发明授权

US4075704A Floating point data processor for high speech operation 失效
标题翻译：浮动点数据处理器，用于高语音操作
公开(公告)号：US4075704A
公开(公告)日：1978-02-21
申请号：US702148
申请日：1976-07-02
申请人： George P. O'Leary
发明人： George P. O'Leary
IPC分类号： G06F7/00 , G06F7/50 , G06F7/52 , G06F7/57 , G06F7/76 , G06F9/38 , G06F7/38
CPC分类号： G06F7/5312 , G06F7/483 , G06F7/485 , G06F7/4876 , G06F7/533 , G06F9/3879 , G06F2207/3884 , G06F2207/3896 , G06F7/49936 , G06F7/49947
摘要： A digital data processor includes a plurality of memory registers, a floating point adder and a floating point multiplier intercoupled by a plurality of simultaneously operable parallel buses facilitating multiple parallel operations during one clock cycle or instruction. The floating adder and multiplier each include a number of stages separated by intermediate temporary storage registers which receive the partial results of a computation for use by the next stage during the next clock period. Floating point additions, multiplications and other arithmetic and logical results are produced during each clock cycle.

89. 发明授权

US3474239A Adder,shifter and logical apparatus 失效
标题翻译： ADDER，SHITER和LOGICAL APPARATUS
公开(公告)号：US3474239A
公开(公告)日：1969-10-21
申请号：US3474239D
申请日：1967-01-13
申请人： IBM
发明人： ALLEN RICHARD G , KURTZ CLARK , MACSORLEY OLIN L , SPENCER DANA R , STETLER WESLEY C
IPC分类号： G06F7/00 , G06F7/50 , G06F7/57 , G06F15/78 , G06F5/02 , G06F7/385 , G06F7/42
CPC分类号： G06F7/57 , G06F7/00 , G06F7/483 , G06F7/4873 , G06F7/4991 , G06F7/49936 , G06F7/508 , G06F15/78 , G06F2207/3824

90. 发明授权

US3460095A Method of using an arithmetic calculator and calculating machine for utilizing said method 失效
标题翻译：使用算术计算器和计算机使用方法
公开(公告)号：US3460095A
公开(公告)日：1969-08-05
申请号：US3460095D
申请日：1966-02-28
申请人： CENTRE NAT RECH SCIENT
发明人： CAROUSSOS PANAYOTIS
IPC分类号： G06F7/487 , G06F7/50 , G06F7/52 , H03M7/24 , G11B13/00 , G06F1/00
CPC分类号： G06F7/4876 , G06F7/485 , G06F7/49936 , H03M7/24

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