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1. 发明授权

US5436858A Decimation circuit and method for filtering quantized signals while providing phase angle correction with a substantially linear phase response 失效
标题翻译：抽取电路和滤波量化信号的方法，同时提供具有基本线性相位响应的相位角校正
公开(公告)号：US5436858A
公开(公告)日：1995-07-25
申请号：US223195
申请日：1994-04-05
申请人： Daniel A. Staver
发明人： Daniel A. Staver
IPC分类号： H03H17/04 , G06F17/10
CPC分类号： H03H17/045 , H03H17/04
摘要： A decimation circuit for filtering a stream of quantized electrical signals while providing phase angle correction and a substantially linear phase response over a predetermined passband range F.sub.B is provided. The stream of quantized electrical signals arrives at a predetermined rate F.sub.M from an oversampling delta-sigma modulator. The decimation circuit includes a decimation filter for filtering the stream of quantized electrical signals to provide a filtered output signal at an output ram F'.sub.S defined by F'.sub.S =F.sub.M /R wherein R is a positive integer. A phase corrector is coupled to the decimation filter to receive the filtered output signal and to correct the phase angle of the received filtered signal so as to provide an equalized phase angle at least over the predetermined range F.sub.B. The value for R is selected such that output rate F'.sub.S is sufficiently situated above bandpass range F.sub.B such that the phase corrector provides a desired substantially linear phase response over the passband range F.sub.B.
摘要翻译：提供一种用于对量化电信号流进行滤波的抽取电路，同时提供相位角校正和在预定通带范围FB上的基本上线性的相位响应。量化电信号流从过采样Δ-Σ调制器到达预定速率FM。抽取电路包括抽取滤波器，用于对量化电信号流进行滤波，以在由F'S = FM / R定义的输出压脚F'处提供滤波输出信号，其中R是正整数。相位校正器耦合到抽取滤波器以接收滤波后的输出信号并校正接收到的滤波信号的相位角，从而至少在预定范围FB上提供均衡的相位角。选择R的值使得输出速率F'S充分地位于带通范围FB之上，使得相位校正器在通带范围FB上提供期望的基本上线性的相位响应。

2. 发明授权

US07269239B2 Simple two-wire communication protocol with feedback status 有权
标题翻译：简单的双线通信协议，具有反馈状态
公开(公告)号：US07269239B2
公开(公告)日：2007-09-11
申请号：US10208014
申请日：2002-07-31
申请人： Daniel A Staver , Bruce Carl Wall , Tue Tran
发明人： Daniel A Staver , Bruce Carl Wall , Tue Tran
IPC分类号： H04L7/00
CPC分类号： G06F13/4291
摘要： A two-wire communication protocol between a controller device and a controlled device, wherein both devices are coupled by a clock line and a data line. The controller device sends control signals comprising N bits, N being greater than or equal to two, to the controlled device via the data line. Each bit of said control signals is latched onto the controlled device on consecutive edges of a clock signal sent by the controller device to the controlled device on the clock line.
摘要翻译：控制器设备和受控设备之间的两线通信协议，其中两个设备通过时钟线和数据线耦合。控制器设备通过数据线将受控设备的N位，N大于或等于2的控制信号发送给受控设备。所述控制信号的每一位在控制装置的时钟信号的连续边缘上锁存在受控装置上，时钟信号由时钟线发送到受控装置。

3. 发明授权

US06681011B1 Method and modem circuit using a dither signal for determining connection status of a phone line 失效
标题翻译：使用抖动信号的方法和调制解调器电路来确定电话线路的连接状态
公开(公告)号：US06681011B1
公开(公告)日：2004-01-20
申请号：US09546849
申请日：2000-04-11
申请人： Daniel A. Staver , Glen W. Brooksby
发明人： Daniel A. Staver , Glen W. Brooksby
IPC分类号： H04M100
CPC分类号： H04M1/82
摘要： A circuit and method for determining connection status of a phone line shared by multiple telecommunications devices, such as modems and phones, are provided. The phone line includes respective tip and ring lines. The circuit comprises a first operational amplifier coupled to receive a signal indicative of a voltage difference between the respective tip and ring lines. The circuit further comprises a lag network coupled to impart a predetermined delay to the output signal from the first operational amplifier. A second operational amplifier is coupled to receive the voltage difference signal. The output signal from the second operational amplifier has a sufficiently fast time response relative to the output signal from the lag network.
摘要翻译：提供了用于确定由诸如调制解调器和电话的多个电信设备共享的电话线路的连接状态的电路和方法。电话线包括各自的尖端和环形线。电路包括耦合以接收指示相应尖端和环线之间的电压差的信号的第一运算放大器。该电路还包括耦合以向来自第一运算放大器的输出信号施加预定延迟的滞后网络。第二运算放大器被耦合以接收电压差信号。来自第二运算放大器的输出信号相对于来自滞后网络的输出信号具有足够快的时间响应。

4. 发明授权

US5548540A Decimation filter having a selectable decimation ratio 失效
标题翻译：具有可选择抽取比率的抽取滤波器
公开(公告)号：US5548540A
公开(公告)日：1996-08-20
申请号：US265475
申请日：1994-06-24
申请人： Daniel A. Staver , Donald T. McGrath
发明人： Daniel A. Staver , Donald T. McGrath
IPC分类号： H03H17/06 , G06F15/31
CPC分类号： H03H17/0664
摘要： A decimation filter for filtering an externally derived stream of quantized electrical signals having a predetermined rate includes a coefficient generator responsive to a set of externally derived decimation-ratio select signals to provide a separate normalized coefficient signal at each respective one of a plurality of output ports. An accumulator is coupled to the coefficient generator to receive each normalized coefficient signal generated therein. The accumulator receives the stream of quantized electrical signals so as to produce, upon masking with respective ones of the received normalized coefficient signals, a plurality of accumulator output signals. An overflow detector is coupled to the accumulator to detect and correct any overflow condition arising in the accumulator.
摘要翻译：用于对具有预定速率的外部导出的量化电信号流进行滤波的抽取滤波器包括响应于一组外部推出的抽取比选择信号的系数发生器，以在多个输出端口中的每个相应的一个输出端口处提供单独的归一化系数信号。累加器耦合到系数发生器以接收其中产生的每个归一化系数信号。累加器接收量化电信号流，以便在接收到的归一化系数信号中的相应的一个被掩蔽时产生多个累加器输出信号。溢流检测器耦合到蓄电池，以检测和校正蓄电池中产生的任何溢出状况。

5. 发明授权

US5111421A System for performing addition and subtraction of signed magnitude floating point binary numbers 失效
标题翻译：用于执行带符号幅值浮点数二进制数加法和减法的系统
公开(公告)号：US5111421A
公开(公告)日：1992-05-05
申请号：US484752
申请日：1990-02-26
申请人： Karl J. Molnar , Ho Chung-Yih , Daniel A. Staver , Barbara D. Molnar
发明人： Karl J. Molnar , Ho Chung-Yih , Daniel A. Staver , Barbara D. Molnar
IPC分类号： G06F7/485 , G06F7/50
CPC分类号： G06F7/485 , G06F2207/3884 , G06F7/49915 , G06F7/49936 , G06F7/49947
摘要： A versatile floating point adder which performs high speed floating point addition or subtraction on operands supplied in a signed magnitude format includes separate exponent and mantissa data paths for processing the exponent fields and mantissa fields of the floating point binary numbers to be added or subtracted. The exponent data path computes the absolute difference between the exponents of the floating point numbers, passes the large exponent, and adjusts the large exponent by an amount needed to normalize the mantissa and to reflect an overflow in the mantissa addition/substration and mantissa rounding operations. The mantissa data path denormalizes one of the input mantissas, adds the two mantissas after the denormalization operation, post-normalizes the resulting mantissa, and rounds the mantissa to the correct precision.
摘要翻译：在以有限幅度格式提供的操作数上执行高速浮点加法或减法的通用浮点加法器包括用于处理要加或减的浮点二进制数的指数字段和尾数字段的独立指数和尾数数据路径。指数数据路径计算浮点数的指数之间的绝对差，通过大指数，并将大指数调整为使尾数归一化所需的量，并反映尾数加法/子空间和尾数舍入操作中的溢出。尾数数据路径对一个输入尾数进行非标准化，在非归一化操作之后添加两个尾数，对所得到的尾数进行后归一化，并将尾数舍入到正确的精度。

6. 发明授权

US4841467A Architecture to implement floating point multiply/accumulate operations 失效
标题翻译：架构实现浮点乘法/累加运算
公开(公告)号：US4841467A
公开(公告)日：1989-06-20
申请号：US104453
申请日：1987-10-05
申请人： Chung-Yih Ho , Karl J. Molnar , Daniel A. Staver
发明人： Chung-Yih Ho , Karl J. Molnar , Daniel A. Staver
IPC分类号： G06F7/485 , G06F7/50 , G06F7/544
CPC分类号： G06F7/485 , G06F7/5443 , G06F2207/3884 , G06F7/49936
摘要： A multiply/accumulator chip architecture capable of operating at a 20 megahertz system clock rate is designed so as to accept floating point numbers in sign magnitude form, to compute a product of the fractional portions thereof and to convert the fractional result into two's complement form for accumulation with the results of a previous product. This architecture readily permits the computation of vector-type inner product operations in a high speed pipelined fashion. Additionally, leading zero's and leadings one's detection is carried out in a multiply parallel fashion so as to rapidly produce post normalization results from the additive portion of the system. The system is implementable on a single integrated circuit chip in which an array multiplier is present so as to minimize inter-chip delays. The architecture of the present invention provides a high speed floating point multiply and accumulate operation with a short pipeline latency.
摘要翻译：设计能够以20兆赫系统时钟速率运行的乘法/累加器芯片架构，以便以符号幅度形式接受浮点数，计算其分数部分的乘积，并将分数结果转换成二进制补码形式，以便积累与以前的产品的结果。该架构容易地以高速流水线方式计算向量式内积运算。另外，领先的零和领先的检测是以并行的方式进行的，以便从系统的添加部分快速产生后归一化结果。该系统可以在单个集成电路芯片上实现，其中存在阵列乘法器以便最小化芯片间延迟。本发明的架构提供了一种具有短流水线延迟的高速浮点乘法和累加运算。

7. 发明授权

US5589766A Field-testable integrated circuit and method of testing 失效
标题翻译：现场可测集成电路和测试方法
公开(公告)号：US5589766A
公开(公告)日：1996-12-31
申请号：US417576
申请日：1995-04-06
申请人： Paul A. Frank , Donald T. McGrath , Daniel A. Staver
发明人： Paul A. Frank , Donald T. McGrath , Daniel A. Staver
IPC分类号： G01R31/28 , G01R31/02
CPC分类号： G01R31/2884
摘要： A field-testable integrated circuit that includes a plurality of analog signal channels for receiving a respective analog signal during a normal mode of operation is provided. Individual test circuits are built-in within the integrated circuit for selecting respective ones of the plurality of channels to receive predetermined reference signals during a test mode of operation while uninterruptedly providing the normal mode of operation in any remaining unselected channels. Each test circuit includes a channel decoder responsive to predetermined channel select signals for producing a respective channel decoder output signal. A multiplexer is responsive to predetermined reference select signals and to the decoder output signal for supplying during the test mode of operation a selected one of the predetermined reference signals to the respective analog channel being coupled to the individual test circuit therein. A switching gate is responsive to the respective channel decoder output signal so that during the normal mode of operation the switching gate is in a respective conducting state for allowing the respective analog signal to pass therethrough while during the test mode of operation the switching gate is in a respective nonconductive state for interrupting the respective analog signal from passing therethrough.
摘要翻译：提供一种现场测试集成电路，其包括用于在正常操作模式期间接收相应模拟信号的多个模拟信号通道。单个测试电路内置在集成电路内，用于选择多个通道中的相应通道以在测试操作模式期间接收预定的参考信号，同时在任何剩余的未选择的通道中不间断地提供正常操作模式。每个测试电路包括响应于预定信道选择信号的信道解码器，以产生相应的信道解码器输出信号。多路复用器响应于预定的参考选择信号和解码器输出信号，以在测试操作模式期间将选定的一个预定参考信号提供给相应的模拟通道，耦合到各个测试电路。开关门响应于相应的通道解码器输出信号，使得在正常操作模式期间，开关门处于相应的导通状态，以允许相应的模拟信号通过，而在测试操作模式期间，开关门处于用于中断相应的模拟信号从而通过的相应的非导通状态。

8. 发明授权

US5463569A Decimation filter using a zero-fill circuit for providing a selectable decimation ratio 失效
标题翻译：抽取滤波器使用零填充电路提供可选择的抽取比例
公开(公告)号：US5463569A
公开(公告)日：1995-10-31
申请号：US265343
申请日：1994-06-24
申请人： Daniel A. Staver , Donald T. McGrath
发明人： Daniel A. Staver , Donald T. McGrath
IPC分类号： H03H17/06 , G06F15/31
CPC分类号： H03H17/0664
摘要： A decimation filter for filtering an externally derived stream of quantized electrical signals includes a coefficient generator responsive to a set of externally derived decimation-ratio select signals to provide a separate normalized coefficient signal at each respective one of a plurality of output ports. The coefficient generator employs a zero-fill circuit comprising first and second circuits which selectively ripple therethrough an scaling-control output signal from a demultiplexer unit in order to provide the normalized coefficient signals. An accumulator is coupled to the coefficient generator to receive each normalized coefficient signal generated therein. The accumulator receives the stream of quantized electrical signals so as to produce, upon masking with respective ones of the received normalized coefficient signals, a plurality of accumulator output signals. An overflow detector is coupled to the accumulator to detect and correct any overflow condition arising in the accumulator.
摘要翻译：用于对外部导出的量化电信号流进行滤波的抽取滤波器包括响应于一组外部导出的抽取比选择信号的系数发生器，以在多个输出端口中的每个相应的一个输出端口处提供单独的归一化系数信号。系数发生器采用零填充电路，该零填充电路包括第一和第二电路，其选择性地从多路分解器单元中纹波通过缩放控制输出信号，以便提供归一化的系数信号。累加器耦合到系数发生器以接收其中产生的每个归一化系数信号。累加器接收量化电信号流，以便在接收到的归一化系数信号中的相应的一个被掩蔽时产生多个累加器输出信号。溢流检测器耦合到蓄电池，以检测和校正蓄电池中产生的任何溢出状况。

9. 发明授权

US5001647A Inertial transformation matrix generator 失效
标题翻译：惯性转换矩阵发生器
公开(公告)号：US5001647A
公开(公告)日：1991-03-19
申请号：US401372
申请日：1989-08-31
申请人： Stephen J. Rapiejko , David S. Chan , Daniel A. Staver , Nancy M. Clark
发明人： Stephen J. Rapiejko , David S. Chan , Daniel A. Staver , Nancy M. Clark
IPC分类号： B60R16/02 , B64C17/02 , G01C21/16 , G06F7/548
CPC分类号： G01C21/16
摘要： An inertial transformation matrix generator generates a succession of Euler transformation matrices in inertial coordinates, and is useful for converting to inertial coordinates the responses of a sensor hard mounted on the hull of a craft (e.g., an aircraft). First, second and third rate-sensing gyros located proximately to said sensor are strapped down to the craft hull, and are oriented to sense the motion of the craft hull in three mutually orthogonal directions, for providing respective output signals indicative of components of craft hull motion in each of those three mutually orthogonal directions. The output signals of the gyros are digitized, and based on these digital signals successive incremental Euler transformation matrices are generated. Each successive incremental Euler transformation matrix and a respective other matrix are multiplied together to generate a respective product matrix, said other matrix initially being a initialization matrix and thereafter being the previously calculated Euler transformation matrix. Each successive current Euler transformation matrix is formed from each successive product matrix, which is done in preferred embodiments of the invention by adding to it at selected times a correction matrix derived by long term comparison of the matrices generated by the inertial transformation matrix generator and the inertial navigation system of the craft.

10. 发明授权

US06173236B2 Vector electricity meters and associated vector electricity metering methods 失效
标题翻译：矢量电表和相关矢量电计量方法
公开(公告)号：US06173236B2
公开(公告)日：2001-01-09
申请号：US08872034
申请日：1997-06-10
申请人： David D. Elmore , Daniel A. Staver
发明人： David D. Elmore , Daniel A. Staver
IPC分类号： G01R2500
CPC分类号： G01R21/1331
摘要： Line voltage and line current signals are sensed on a power line having at least one conducting path. The sensed line voltages and line currents are converted into a digital signal. A phase-to-neutral voltage signal and phase current signal are computed from the digital signal to thereby define a phase of the power line. An interval of orthogonality is determined from the sensed voltage and current signals, coinciding with passage of an integral number of cycles of a fundamental frequency reference signal which is computed from the computed phase-to-neutral voltage signal. A vector metering quantity is computed for the determined interval of orthogonality from the computed phase-to-neutral voltage signal and the computed phase current signal. The vector metering quantities to be computed may be identified and computed based upon an associated detent. The vector metering quantity is also computed based on an identified circuit topology.
摘要翻译：在具有至少一个导电路径的电力线上检测线电压和线电流信号。感测到的线路电压和线路电流被转换为数字信号。从数字信号计算出相电压中性点电压信号和相电流信号，从而定义电力线的相位。从感测的电压和电流信号确定正交性的间隔，其与从计算出的相电压信号计算的基频信号的整数倍的循环相一致。根据计算的相电压信号和计算出的相电流信号，计算确定的正交间隔的向量计量量。可以基于相关联的制动器来识别和计算要计算的矢量计量量。也可以基于所识别的电路拓扑来计算矢量测量量。

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