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    • 1. 发明授权
    • Architecture to implement floating point multiply/accumulate operations
    • 架构实现浮点乘法/累加运算
    • US4841467A
    • 1989-06-20
    • US104453
    • 1987-10-05
    • Chung-Yih HoKarl J. MolnarDaniel A. Staver
    • Chung-Yih HoKarl J. MolnarDaniel A. Staver
    • G06F7/485G06F7/50G06F7/544
    • G06F7/485G06F7/5443G06F2207/3884G06F7/49936
    • A multiply/accumulator chip architecture capable of operating at a 20 megahertz system clock rate is designed so as to accept floating point numbers in sign magnitude form, to compute a product of the fractional portions thereof and to convert the fractional result into two's complement form for accumulation with the results of a previous product. This architecture readily permits the computation of vector-type inner product operations in a high speed pipelined fashion. Additionally, leading zero's and leadings one's detection is carried out in a multiply parallel fashion so as to rapidly produce post normalization results from the additive portion of the system. The system is implementable on a single integrated circuit chip in which an array multiplier is present so as to minimize inter-chip delays. The architecture of the present invention provides a high speed floating point multiply and accumulate operation with a short pipeline latency.
    • 设计能够以20兆赫系统时钟速率运行的乘法/累加器芯片架构,以便以符号幅度形式接受浮点数,计算其分数部分的乘积,并将分数结果转换成二进制补码形式,以便 积累与以前的产品的结果。 该架构容易地以高速流水线方式计算向量式内积运算。 另外,领先的零和领先的检测是以并行的方式进行的,以便从系统的添加部分快速产生后归一化结果。 该系统可以在单个集成电路芯片上实现,其中存在阵列乘法器以便最小化芯片间延迟。 本发明的架构提供了一种具有短流水线延迟的高速浮点乘法和累加运算。
    • 2. 发明授权
    • Versatile data shifter with sticky bit generation capability
    • 具有粘性位生成功能的多功能数据移位器
    • US4901263A
    • 1990-02-13
    • US243359
    • 1988-09-12
    • Chung-Yih HoKarl J. MolnarDaniel A. Staver
    • Chung-Yih HoKarl J. MolnarDaniel A. Staver
    • G06F5/01
    • G06F5/012G06F7/49952
    • A barrel-shift data shifter structure is modified to segregate switches in a switching matrix included therein into those switches as participate in a simple shift as well as in a barrel shift and those switches used only in a barrel shift. The former set of switches is controlled by shift control signals alone, and the latter set of switches responds to shift control signals and to the presence or absence of a rotation enable signal. The number of switches required is substantially smaller than required in a barrel shifter followed in cascade by a simple data shifter. Preferably provision is made for sticky bit generation. The sticky bit is the LOGIC OR response to all bits shifted to less significance than output data.
    • 修改桶形移位数据移位器结构以将其中包括的开关矩阵中的开关分离为参与简单移位以及桶位移动的那些开关,以及仅在桶形移位中使用的开关。 前一组开关由单独的换档控制信号控制,后一组开关响应换档控制信号以及是否有旋转使能信号。 所需的开关数量明显小于桶形移位器中所需的开关数量,然后由简单的数据移位器级联。 优选地设置用于产生粘性位。 粘性位是对所有位的LOGIC OR响应移位到比输出数据更小的意义。
    • 5. 发明申请
    • CHANNEL STATE INFORMATION REPORTING FOR A SUCCESSIVELY DECODED, PRECODED MULTI-ANTENNA TRANSMISSION
    • 通道状态信息报告,用于下一代已解码的多天线传输
    • US20120069833A1
    • 2012-03-22
    • US12883482
    • 2010-09-16
    • Karl J. Molnar
    • Karl J. Molnar
    • H04B7/216
    • H04L1/0023H04B7/0626H04B7/063H04B7/0639H04B7/0658H04L1/0045H04L25/03
    • Teachings herein provide reduced complexity channel state information (CSI) reporting for a successively decoded, precoded multi-antenna transmission. A wireless communication device reports CSI by forming, for each candidate transmission rank of the transmission, a sequence of codewords by iteratively adding codewords allowed for that rank to the sequence. At any given point in the sequence, the device adds the codeword expected to yield the highest individual information rate if decoded at that point in the sequence, considering the different rates possible under different precodings of the transmission. The device then computes, for each rank, a sum information rate across the codewords in the sequence formed for that rank, selects the rank having the highest sum information rate, and reports the selected rank along with the sequence formed for that rank. CSI reporting complexity is reduced because the device constrains its evaluation to only some of the possible decoding sequences.
    • 这里的教导为连续解码的预编码的多天线传输提供了降低复杂度的信道状态信息(CSI)报告。 无线通信设备通过向该序列迭代地添加允许该等级的码字,为传输的每个候选传输等级形成码字序列来报告CSI。 在序列中的任何给定点处,考虑到在传输的不同预编码下可能的不同速率,设备将预期的码字添加以产生最高个体信息速率,如果在序列中的那一点被解码。 然后,该装置针对每个等级计算在为该等级形成的序列中的码字之间的和信息速率,选择具有最高和信息速率的秩,并且将所选择的等级与为该等级形成的序列一起报告。 由于设备将其评估限制为只有一些可能的解码序列,因此CSI报告复杂度降低。
    • 7. 发明授权
    • Overlapping slot transmission using phased arrays
    • 使用相控阵列重叠槽传输
    • US06490261B1
    • 2002-12-03
    • US09429463
    • 1999-10-28
    • Paul W. DentKarl J. Molnar
    • Paul W. DentKarl J. Molnar
    • H04J300
    • H04W52/42H04B7/0408H04B7/06
    • A time-division multiple access (TDMA) base station is disclosed for preserving across-slot signal continuity of signals transmitted in different directions on a given frequency. The base station includes a multi-directional antenna for radiating signals. A processor is operatively coupled to the antenna for generating a first data signal for a first time slot of a TDMA frame including a first pre-determined symbol pattern and a second pre-determined symbol pattern, for generating a second data signal for a second time slot of the TDMA frame including the second predetermined symbol pattern, and for communicating the first data signal and the second data signal to the antenna such that the first data signal is radiated in a first direction and the second data signal is radiated in a second direction. The first data signal is modulated at a first phase for transmission in the first time slot at a first power level in the first direction on the given frequency. The second data signal is modulated at a second phase for transmission in the second time slot at a second power level in the second direction on the given frequency.
    • 公开了一种用于在给定频率上保持在不同方向上发射的信号的跨时隙信号连续性的时分多址(TDMA)基站。 基站包括用于辐射信号的多向天线。 处理器可操作地耦合到天线,用于产生包括第一预定符号模式和第二预定符号模式的TDMA帧的第一时隙的第一数据信号,用于第二次产生第二数据信号 包括第二预定符号模式的TDMA帧的时隙,并且用于将第一数据信号和第二数据信号传送到天线,使得第一数据信号沿第一方向辐射,并且第二数据信号沿第二方向辐射 。 第一数据信号在第一阶段被调制,以在给定频率上的第一方向上的第一功率电平在第一时隙中传输。 第二数据信号在第二阶段被调制,以在给定频率上的第二方向上以第二功率电平在第二时隙中传输。
    • 8. 发明授权
    • Methods and systems for reducing co-channel interference using multiple timings for a received signal
    • 用于使用接收信号的多个定时来减少同信道干扰的方法和系统
    • US06304618B1
    • 2001-10-16
    • US09143821
    • 1998-08-31
    • Abdulrauf HafeezKarl J. MolnarGregory E. Bottomley
    • Abdulrauf HafeezKarl J. MolnarGregory E. Bottomley
    • H03D100
    • H04L25/03337H04L25/0204
    • A plurality of timings are estimated for a received signal wherein the plurality of timings correspond to a plurality of transmitted signals. The received signal is then sampled in accordance with the plurality of timings, to produce a plurality of sample streams from the received signal. Channel estimates are produced for the plurality of transmitted signals and metrics are computed using the sample streams and the channel estimates. Information symbols corresponding to the transmitted signals are detected by using the metrics. Accordingly, by using multiple timings for a received signal, rather than using a common timing, the number of channel taps that are used may be reduced and the accuracy of symbol detection may be increased. The channel estimates may be produced by generating pulse-shape information and producing channel estimates for the multiple transmitted signals using the received signal and the pulse-shape information. Channel estimates may be produced that correspond to a plurality of symbol sequence hypotheses. Channel estimates may be updated using an error signal.
    • 针对接收信号估计多个定时,其中多个定时对应于多个发送信号。 然后根据多个定时对接收到的信号进行采样,以从接收信号产生多个采样流。 对于多个发送信号产生信道估计,并且使用采样流和信道估计来计算度量。 通过使用度量来检测对应于所发送的信号的信息符号。 因此,通过对接收到的信号使用多个定时,而不是使用公共定时,可以减少使用的信道抽头的数量,并且可以增加符号检测的精度。 可以通过使用接收信号和脉冲形状信息产生脉冲形状信息并产生多个发送信号的信道估计来产生信道估计。 可以产生对应于多个符号序列假设的信道估计。 可以使用错误信号来更新信道估计。