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81. 发明授权

US5692136A Multi-processor system including priority arbitrator for arbitrating request issued from processors 失效
标题翻译：多处理器系统包括用于仲裁从处理器发出的请求的优先仲裁器
公开(公告)号：US5692136A
公开(公告)日：1997-11-25
申请号：US685748
申请日：1996-07-24
申请人： Yuuki Date , Masanobu Inaba
发明人： Yuuki Date , Masanobu Inaba
IPC分类号： G06F13/14 , G06F13/368 , G06F15/17 , G06F13/00
CPC分类号： G06F13/14 , G06F13/368 , G06F15/17
摘要： In a multi-processor system, a priority arbitrator receives a request issued from each of processors, and arbitrates conflicts occurring among the requests. The requests derived from the respective processors are inputted via selectors to fixed priority arbitrating circuits. Only one request is selected by the fixed priority arbitrating circuit, and the selected request is held in an output register. The pending request is detected by an AND circuit, and the detection result is held in a pending register. When there is such a request held in the pending register, the subsequent request is not selected by the selector. The priorities of the plural fixed priority arbitrating circuits within the multi-processor system may be made different from each other, depending upon the use conditions of the multi-processor system.
摘要翻译：在多处理器系统中，优先级仲裁器接收从每个处理器发出的请求，并且仲裁在请求之间发生的冲突。从各处理器得到的请求通过选择器输入到固定优先级仲裁电路。固定优先级仲裁电路仅选择一个请求，所选择的请求保存在输出寄存器中。待机请求由AND电路检测，检测结果保持在挂起的寄存器中。当待处理寄存器中存在这样的请求时，选择器不会选择后续请求。根据多处理器系统的使用条件，多处理器系统内的多个固定优先级仲裁电路的优先级可以彼此不同。

82. 发明授权

US5659689A Method and apparatus for transmitting information on a wired-or bus 失效
标题翻译：用于在有线或总线上传输信息的方法和装置
公开(公告)号：US5659689A
公开(公告)日：1997-08-19
申请号：US206091
申请日：1994-03-01
申请人： Nitin Sarangdhar , Samuel E. Calvin
发明人： Nitin Sarangdhar , Samuel E. Calvin
IPC分类号： G06F13/368 , G06F13/38 , G06F13/40
CPC分类号： G06F13/368
摘要： A method and apparatus for use in transmitting information on a wired-OR signal line is described which employs a data transfer protocol exploiting the generally shorter signal settling time occurring following high to low signal voltage transitions than occurs following low to high signal voltage transitions. In accordance with the protocol, the transmission of meaningful information on multiple-driver signal lines is restricted to the assertion of high to low signal voltage transitions. By asserting meaningful information only on high to low transitions, the clock period for the bus may be set based on the voltage settling time resulting from only high to low transitions rather than from arbitrary transitions. As a result, the transmission of meaningful signals are all within the limits of incident wave switching and a high overall information transmission rate is achieved. The amount of information transferable per clock cycle depends upon whether the wired-OR signal line is a single driver line, a multiple driver line wherein events are correlated with commonly observable events, or a multiple driver line wherein events are not correlated with commonly observable events. For single driver lines, one unit of information per clock cycle may be transmitted. For multiple driver lines which are correlated with commonly observable events, one unit of information may be transmitted every two clock cycles. For multiple driver lines which are not correlated with commonly observable events, one unit of information per three clock cycles may be transmitted. Method and apparatus embodiments of the invention are described in particular with reference to a multiprocessor computer system having a latched wired-OR bus.
摘要翻译：描述了一种用于在有线或信号线上传输信息的方法和装置，其采用数据传输协议，该数据传输协议利用在低至高信号电压转换之后出现的高到低信号电压转换之后出现的大体上较短的信号建立时间。根据协议，传输有关多驱动器信号线的有意义的信息被限制在高到低信号电压转换的断言。通过仅在高到低转换时断言有意义的信息，总线的时钟周期可以基于仅由高到低转换而不是从任意转换产生的电压稳定时间来设置。结果，有意义的信号的传输都在入射波切换的限度内，并且实现了高的总体信息传输速率。每个时钟周期可传输的信息量取决于有线信号线是单个驱动器线，其中事件与常见可观察事件相关联的多驱动器线，或多个驱动器线，其中事件与常见的可观察事件不相关。对于单个驱动器线，可以传送每个时钟周期的一个单位信息。对于与常见可观察事件相关的多个驱动线路，可以每两个时钟周期传输一个信息单元。对于与常见可观察事件不相关的多个驱动线路，可以传输每三个时钟周期的一个信息单位。具体参考具有锁存的有线或/或总线的多处理器计算机系统来描述本发明的方法和设备实施例。

83. 发明授权

US5507032A Multiprocessor I/O request control system forming device drive queue and processor interrupt queue from rows and cells of I/O request table and interrupt request table 失效
标题翻译：多处理器I / O请求控制系统从I / O请求表和中断请求表的行和单元格形成设备驱动队列和处理器中断队列
公开(公告)号：US5507032A
公开(公告)日：1996-04-09
申请号：US166799
申请日：1993-12-02
申请人： Makoto Kimura
发明人： Makoto Kimura
IPC分类号： G06F13/368 , G06F13/42 , G06F15/17 , G06F13/00 , G06F9/46 , G06F13/12
CPC分类号： G06F13/368 , G06F13/4221 , G06F15/17
摘要： An input/output request control system in a multi-processor system includes a plurality of information processing modules (PM). The system comprises a plurality of input/output adapters (ADP) commonly used by each of said information processing modules and a plurality of input/output devices (DVC) divided into groups, each group controlled by one of the input/output adapters. An input/output request maintaining table (LDVC) manages input/output requests from respective information processing modules for each of the input/output devices controlled by said information processing modules by using a queue. Input/output requests from respective information processing modules are processed based on the state of the input/output request maintaining table and the input/output devices.
摘要翻译：多处理器系统中的输入/输出请求控制系统包括多个信息处理模块（PM）。该系统包括由每个所述信息处理模块通常使用的多个输入/输出适配器（ADP）和被分成组的多个输入/输出设备（DVC），每个组由输入/输出适配器之一控制。输入/输出请求维护表（LDVC）通过使用队列来管理由所述信息处理模块控制的每个输入/输出设备的各个信息处理模块的输入/输出请求。根据输入/输出请求维护表和输入/输出设备的状态来处理来自相应信息处理模块的输入/输出请求。

84. 发明授权

US5388215A Uncoupling a central processing unit from its associated hardware for interaction with data handling apparatus alien to the operating system controlling said unit and hardware 失效
标题翻译：从其相关联的硬件解耦中央处理单元，用于与控制所述单元和硬件的操作系统不相关的数据处理装置进行交互
公开(公告)号：US5388215A
公开(公告)日：1995-02-07
申请号：US234706
申请日：1994-04-28
申请人： Ernest D. Baker , John M. Dinwiddie, Jr. , Lonnie E. Grice , James M. Joyce , John M. Loffredo , Kenneth R. Sanderson
发明人： Ernest D. Baker , John M. Dinwiddie, Jr. , Lonnie E. Grice , James M. Joyce , John M. Loffredo , Kenneth R. Sanderson
IPC分类号： G06F15/16 , G06F9/46 , G06F11/00 , G06F11/16 , G06F11/20 , G06F12/02 , G06F13/368 , G06F15/177 , G06F15/20
CPC分类号： G06F11/1658 , G06F11/1641 , G06F11/1679 , G06F12/023 , G06F12/0284 , G06F13/368 , G06F11/1608 , G06F11/1616 , G06F11/1625 , G06F11/1633
摘要： The functions of two virtual operating systems (e. S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors access the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.
摘要翻译：两个虚拟操作系统（例如S / 370 VM，VSE或IX370和S / 88 OS）的功能被合并到一个物理系统中。 S / 88处理器的合作伙伴对运行S / 88操作系统，并处理系统的容错和单系统映像方面。 S / 370处理器的一个或多个伙伴对直接和通过S / 88总线耦合到对应的S / 88处理器。每个S / 370处理器从S / 88主存储器分配从1到16兆字节的连续存储。每个S / 370虚拟操作系统认为其存储器分配从地址0开始，并且通过正常的S / 370动态存储器分配和寻呼技术管理其存储器。 S / 370被限制检查以防止S / 370访问S / 88存储器空间。 S / 88操作系统是所有系统硬件和I / O设备的主控。 S / 88处理器直接响应S / 88应用程序来访问S / 370地址空间，以便S / 88可以将I / O数据移动到S / 370 I / O缓冲器中并处理S / 370 I / O操作。 S / 88和S / 370对等体处理器对在单个系统环境中执行其各自的操作系统，而不会显着地重写任一操作系统。操作系统都不知道其他操作系统和其他处理器对。

85. 发明授权

US5371893A Look-ahead priority arbitration system and method 失效
标题翻译：先行优先仲裁系统和方法
公开(公告)号：US5371893A
公开(公告)日：1994-12-06
申请号：US816358
申请日：1991-12-27
申请人： Donald W. Price , Forrest A. Reiley , William K. Rodiger
发明人： Donald W. Price , Forrest A. Reiley , William K. Rodiger
IPC分类号： G06F13/362 , G06F13/368 , G06F13/14
CPC分类号： G06F13/368
摘要： An improved arbitration system is disclosed for arbitrating signals at a plurality of input nodes to output nodes where each input node can access any output node. The system includes a FIFO (first-in-first-out) input queue for each node and means for arbitrating the top of each queue for providing the arbitrated output to a given node and means when the top of the input queue has no request for a given node arbitrating the requests from the next to the top entry of the input queues and providing the data from the next to top entry associated with the arbitrated request to the given node.
摘要翻译：公开了一种改进的仲裁系统，用于对多个输入节点处的信号进行仲裁以输出节点，其中每个输入节点可以访问任何输出节点。该系统包括用于每个节点的FIFO（先进先出）输入队列，以及用于仲裁每个队列的顶部以将仲裁的输出提供给给定节点的装置，并且当输入队列的顶部没有请求时给定节点仲裁来自输入队列的下一个到顶部条目的请求，并将与仲裁请求相关联的下一个顶部条目的数据提供给给定节点。

86. 发明授权

US5341501A Processor bus access 失效
标题翻译：处理器总线访问
公开(公告)号：US5341501A
公开(公告)日：1994-08-23
申请号：US771582
申请日：1991-10-04
申请人： James W. Keeley , Richard A. Lemay , Chester M. Nibby, Jr.
发明人： James W. Keeley , Richard A. Lemay , Chester M. Nibby, Jr.
IPC分类号： G06F13/368 , G06F9/46
CPC分类号： G06F13/368
摘要： A high performance microprocessor bus state machine couples to a synchronous local bus in common with another state machine for accessing a local memory according to a preestablished bus protocol. Circuit means cosines the state of a predetermined protocol bus signal indicating the release of the local bus and transitions of the clock signal which are not used for synchronizing the operations of the state machines. The resulting signal applies required address and control signals in advance to the local bus enabling the non-microprocessor state machine to generate the required address strobe to local memory on the next clock which follows the release of the local bus by the microprocessor which eliminates a clock cycle whenever local bus control passes from the microprocessor bus state machine to another state machine.
摘要翻译：高性能微处理器总线状态机根据预先建立的总线协议与另一状态机共同连接到同步局部总线，用于访问本地存储器。电路意味着使指示本地总线的释放和不用于同步状态机的操作的时钟信号的转换的预定的协议总线信号的状态。所产生的信号预先将所需的地址和控制信号施加到本地总线，使得非微处理器状态机能够在微处理器释放本地总线之后的下一个时钟产生所需的地址选通脉冲，从而消除时钟当本地总线控制从微处理器总线状态机传递到另一状态机时，循环。

87. 发明授权

US5305442A Generalized hierarchical architecture for bus adapters 失效
标题翻译：总线适配器的通用分层结构
公开(公告)号：US5305442A
公开(公告)日：1994-04-19
申请号：US858698
申请日：1992-03-27
申请人： Derald A. Pedersen , James A. Dahlberg
发明人： Derald A. Pedersen , James A. Dahlberg
IPC分类号： G06F13/368 , G06F13/40 , G06F13/14
CPC分类号： G06F13/368 , G06F13/4036
摘要： A top state controller controls a bus adapter to a selected master or slave top state in response to a command on a local or system bus during a dispatch state of the bus adapter. The bus adapter remains in the selected top state until the command is completed or suspended, whereupon it returns to the dispatch state. The top state controller sets a first flag upon a change from a master top state to the dispatch state in response to suspension of a command by a data handling device, and sets a second flag upon a change from a slave top state to the dispatch state upon completion of a command. The top state controller is responsive to the first or second flag to operate the bus adapter to that master top state from which the bus adapter changed to set the first flag and is responsive to the completion of the suspended command to clear the first and said second flags. The controlled bus adapter and top state controller permit resolution of deadlock conditions and establish priorities between the local and system buses, and permit suspension of the master states to respond to slave commands.
摘要翻译：在总线适配器的调度状态期间，顶部状态控制器响应于本地或系统总线上的命令，将总线适配器控制到选定的主从或从属状态。总线适配器保持在选定的顶部状态，直到命令完成或暂停，然后返回到调度状态。顶部状态控制器响应于数据处理装置的命令中止而在从主机状态改变到分派状态时设置第一标志，并且在从从顶部状态到分派状态的改变时设置第二标志完成命令后。顶部状态控制器响应于第一或第二标志以将总线适配器操作到总主机适配器改变为主设备顶部状态，以设置第一标志，并且响应于完成暂停的命令以清除第一和第二标志标志受控总线适配器和顶级状态控制器允许解决死锁条件并建立本地和系统总线之间的优先级，并允许中止主状态以响应从机命令。

88. 发明授权

US5289583A Bus master with antilockup and no idle bus cycles 失效
标题翻译：总线主机具有防锁定功能，无空闲总线周期
公开(公告)号：US5289583A
公开(公告)日：1994-02-22
申请号：US600337
申请日：1990-10-19
申请人： Lisa L. Fischer , Stephen D. Hanna
发明人： Lisa L. Fischer , Stephen D. Hanna
IPC分类号： G06F13/28 , G06F13/30 , G06F13/362 , G06F13/368 , G06F13/14
CPC分类号： G06F13/30 , G06F13/368
摘要： Bus master for use in computer system includes logic for determining the number of words remaining to be transferred in a DMA operation to supply signals to permit arbitration to start for the next DMA request, thereby avoiding an idle cycle. A timeout state machine is also included to prevent the bus master state machine from hanging in a state with no exit. Errors can be masked to permit analysis of system problems.
摘要翻译：用于计算机系统的总线主机包括用于确定在DMA操作中剩余要传送的字数的逻辑，以提供信号以允许仲裁开始下一个DMA请求，从而避免空闲周期。还包括一个超时状态机，以防止总线主控状态机挂在没有退出的状态。错误可以被掩盖，以便分析系统问题。

89. 发明授权

US5148545A Bus device which performs protocol confidential transactions 失效
标题翻译：执行协议机密事务的总线设备
公开(公告)号：US5148545A
公开(公告)日：1992-09-15
申请号：US384128
申请日：1989-07-21
申请人： William C. Herbst , Lauren D. Baker , Gary W. Stevens
发明人： William C. Herbst , Lauren D. Baker , Gary W. Stevens
IPC分类号： G06F13/368
CPC分类号： G06F13/368
摘要： A bus device of a first type uses a first arbitration protocol. The first-type device is designed for use in a computer system having a communications bus, and one or more other bus devices connected to the bus, including possible first-type bus devices which also use the first arbitration protocol and one or more second-type bus devices which use a second, different, arbitration protocol. The first-type bus device includes a protocol specific memory for storing information; means for monitoring the bus to determine whether the current bus master of the bus arbitrated in the manner of the first or second arbitration protocols; and means for denying the current bus master the ability to access information stored in the protocol specific memory if the means for monitoring determines the bus master arbitrated according to the second arbitration protocol.
摘要翻译：第一类型的总线装置使用第一仲裁协议。第一类设备被设计用于具有通信总线的计算机系统和连接到总线的一个或多个其它总线设备，包括也可以使用第一仲裁协议的第一类型总线设备和一个或多个第二类型总线设备，使用第二种不同的仲裁协议的总线设备。第一类总线设备包括用于存储信息的协议专用存储器; 用于监视总线的装置，以确定当前总线主控总线以第一或第二仲裁协议的方式进行仲裁; 以及用于如果监视装置确定根据第二仲裁协议仲裁的总线主机，则拒绝当前总线主机访问存储在协议专用存储器中的信息的能力的装置。

90. 发明授权

US4628447A Multi-level arbitration system for decentrally allocating resource priority among individual processing units 失效
标题翻译：用于在各个处理单元之间分散分配资源优先级的多级仲裁系统
公开(公告)号：US4628447A
公开(公告)日：1986-12-09
申请号：US667391
申请日：1984-11-02
申请人： Roger Cartret , Giovanni Volpe
发明人： Roger Cartret , Giovanni Volpe
IPC分类号： G06F13/368 , G06F13/378 , G06F15/16 , G06F13/18
CPC分类号： G06F13/378 , G06F13/368
摘要： A decentralized arbitrator includes an individual elementary arbitrator and a level elementary arbitrator for each arbitration unit. Determination of the priority due to one unit, when no other unit claims priority, is accelerated by directing the request states of all units on the same level and on all other levels to the input of an AND gate, the output of which is connected to the bus-utilization enablement input of the relevant unit, through an OR gate and a D flip-flop.
摘要翻译：分散仲裁员包括每个仲裁单位的个人初级仲裁员和级别初级仲裁员。通过将所有单元的请求状态指向相同级别和所有其他级别的AND门的输入，其输出连接到一个单元，当没有其他单元声明优先级时，确定由于一个单元的优先级相关单元的总线使能启用输入，通过或门和D触发器。

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