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1. 发明授权

US09996488B2 I3C high data rate (HDR) always-on image sensor 8-bit operation indicator and buffer over threshold indicator 有权
公开(公告)号：US09996488B2
公开(公告)日：2018-06-12
申请号：US15246098
申请日：2016-08-24
申请人： QUALCOMM Incorporated
发明人： Shoichiro Sengoku
IPC分类号： G06F13/00 , G06F13/364 , G06F13/16 , G06F13/42 , G06F13/24 , G06F13/378 , G06F13/362
CPC分类号： G06F13/364 , G06F13/1673 , G06F13/24 , G06F13/362 , G06F13/378 , G06F13/4282
摘要： A method for enabling 8-bit data word access over a protocol limited to 16-bit data word access is provided. Data may be encapsulated within the lowest 19 bits of a 20-bit number. If it is ascertained that an 8-bit data word is to be used in a system supporting only 16-bit data word access, a byte-enable indicator may be provided within a most significant bit of the 20-bit number while also allocating an 8-bit data region for transfer of the 8-bit data word. The 20-bit number may then be transcoded into a 12-digit ternary number, wherein a residual numerical region is defined as a number space by which a first numerical region defined for the 12-digit ternary number exceeds a second numerical region defined by the lowest 19 bits of the 20-bit number.

2. 发明授权

US09519603B2 Method and apparatus to enable multiple masters to operate in a single master bus architecture 有权
标题翻译：使多个主机能够在单个主总线架构中运行的方法和装置
公开(公告)号：US09519603B2
公开(公告)日：2016-12-13
申请号：US14480540
申请日：2014-09-08
申请人： QUALCOMM Incorporated
发明人： Shoichiro Sengoku , Richard Dominic Wietfeldt , George Alan Wiley
IPC分类号： G06F13/378 , G06F13/36 , G06F13/24 , G06F13/362
CPC分类号： G06F13/378 , G06F13/24 , G06F13/36 , G06F13/362 , G06F2213/3602
摘要： To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to trigger an IRQ signal over a shared, single line IRQ bus. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ signal. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device.
摘要翻译：为了通过支持单个主器件的总线架构来容纳多个主器件，为非激活主器件提供了通过共享的单线IRQ总线触发IRQ信号的机制。然后当前主机通过共享数据总线轮询其他无效主设备，以确定哪个无效主设备正在断言IRQ信号。当识别出断言无效的主设备时，当前的主设备将数据总线的控制权授予新的主设备，从而使非活动主设备成为新的主主设备。

3. 发明授权

US5617309A Configuration for data transfer with a parallel bus system 失效
标题翻译：使用并行总线系统进行数据传输的配置
公开(公告)号：US5617309A
公开(公告)日：1997-04-01
申请号：US424381
申请日：1995-05-04
申请人： Michael Abert , Siegfried Block , Johannes Bozenhardt , Franz Leigsnering , Werner Pfatteicher , Franz-Clemens Schewe
发明人： Michael Abert , Siegfried Block , Johannes Bozenhardt , Franz Leigsnering , Werner Pfatteicher , Franz-Clemens Schewe
IPC分类号： G06F13/42 , G06F13/14 , G06F13/368 , G06F13/378 , G06F19/00
CPC分类号： G06F13/368 , G06F13/378
摘要： A configuration for data transfer with a parallel bus system including an address bus, a data bus and a control bus and with several units interfacing with them. A first control line is used to send an acknowledge signal with which one or more units addressed by a first unit acknowledge accesses in access cycles. A second control line is used to detect addressing errors and accesses to non-existing units and to carry a signal ready control signal to the first unit from the others indicating whether one of the interfaced units was addressed. To do so, the signal ready control signal has dominant and recessive states. During an access cycle, only addressed units generate a dominant state. The control signal is also used for synchronous multipoint access. The invention can be used in bus systems.
摘要翻译： PCT No.PCT / DE93 / 01037 Sec。 371日期：1995年5月4日 102（e）日期1995年5月4日PCT提交1993年10月29日PCT公布。公开号WO94 / 10631 日期1994年5月11日一种用于并行总线系统的数据传输配置，包括地址总线，数据总线和控制总线，并具有与其连接的多个单元。第一控制线用于发送确认信号，由访问周期中由第一单元寻址的一个或多个单元确认访问。第二控制线用于检测寻址错误和对不存在的单元的访问，并且将来自其他单元的信号就绪控制信号传送到第一单元，指示接口单元之一是否被寻址。为此，信号就绪控制信号具有主导和隐性状态。在访问周期中，只有寻址单元才能产生主导状态。控制信号也用于同步多点接入。本发明可用于公共汽车系统。

4. 发明授权

US5038274A Interrupt servicing and command acknowledgement system using distributed arbitration apparatus and shared bus 失效
标题翻译：使用分布式仲裁设备和共享总线的中断服务和命令确认系统
公开(公告)号：US5038274A
公开(公告)日：1991-08-06
申请号：US437347
申请日：1989-11-15
申请人： Michael J. K. Nielsen
发明人： Michael J. K. Nielsen
IPC分类号： G06F13/378
CPC分类号： G06F13/378
摘要： Each user of an intercommunication bus is associated with a distinct channel of an arbitration bus and maintains a priority record indicating its current priority status against each other user. During a contention interval each user then seeking to use the intercommunication bus bids for use of it by transmitting a bus request signal and makes an analysis of the signals to ascertain if it has dominating priority for initiating a transaction on the bus, and access is granted accordingly. During the use-signal interval a user then using the intercommunication bus transmits an in-use signal used to up-date priority records with the effect of giving the last using user lowest priority. For transactions which require a response from a user other than the one initiating the transaction, a second round of bidding is conducted to determine whether any user is qualified to respond and if so which will be enabled to do so. When the response bidding shows no bidders the system immediately initiates bidding for a new transaction.
摘要翻译：互通总线的每个用户与仲裁总线的不同信道相关联，并且保持指示其对彼此用户的当前优先级状态的优先级记录。在争用间隔期间，每个用户然后寻求使用互通总线出价以通过发送总线请求信号并对信号进行分析，以确定其是否具有在总线上启动交易的主导优先级，并且允许访问相应地。在使用信号间隔期间，用户然后使用互通总线发送用于最新优先级记录的用途信号，具有给予最后使用用户最低优先级的效果。对于需要除了启动交易的用户以外的用户作出回应的交易，进行第二轮投标以确定任何用户是否有资格回应，如果是这样，则可以启用此操作。当响应投标显示没有投标人时，系统立即启动新交易的投标。

5. 发明授权

US4622630A Data processing system having unique bus control protocol 失效
标题翻译：数据处理系统具有独特的总线控制协议
公开(公告)号：US4622630A
公开(公告)日：1986-11-11
申请号：US546514
申请日：1983-10-28
申请人： Chandra R. Vora , Michael L. Ziegler , Mark Bagula , Steve Hamilton
发明人： Chandra R. Vora , Michael L. Ziegler , Mark Bagula , Steve Hamilton
IPC分类号： G06F13/18 , G06F13/37 , G06F13/378 , G06F9/00
CPC分类号： G06F13/37 , G06F13/18 , G06F13/378
摘要： In a data processing system which uses a common bus for communication of address and data information among a plurality of system components, a bus timing technique uses a clock signal having a transfer time period which comprises a plurality of subperiods which requires address transfer to take place during a first selected group of subperiods and data to be transferred during a second selected group of subperiods with idle subperiods in between. A first control signal is generated by the data receiving or data supplying unit in order to inhibit access to the bus until such transfer is completed and a second control signal can be provided to lock-in bus access by such unit if desired for more than one transfer period. Appropriate priority is arranged for bus access among selected system components whether the common bus system has a single bus for use with a single port memory or a dual bus for use with a dual port memory.
摘要翻译：在使用公共总线用于多个系统组件中的地址和数据信息的通信的数据处理系统中，总线定时技术使用具有传输时间段的时钟信号，该时间周期包括要发生地址传送的多个子周期在第一选择的子周期期间和在第二选择的子周期期间要传输的数据，其中在其间具有空闲子周期。第一控制信号由数据接收或数据提供单元产生，以便在这种传输完成之前禁止对总线的访问，并且如果需要多于一个的话可以提供第二控制信号来锁定总线访问转让期。布置适当的优先级，用于所选择的系统组件之间的总线访问，无论公共总线系统是否具有用于单个端口存储器的单个总线或与双端口存储器一起使用的双总线。

6. 发明授权

US4559595A Distributed priority network logic for allowing a low priority unit to reside in a high priority position 失效
标题翻译：用于允许低优先级单元驻留在高优先级位置的分布式优先级网络逻辑
公开(公告)号：US4559595A
公开(公告)日：1985-12-17
申请号：US453406
申请日：1982-12-27
申请人： Daniel A. Boudreau , Edward R. Salas , James M. Sandini
发明人： Daniel A. Boudreau , Edward R. Salas , James M. Sandini
IPC分类号： G06F3/00 , G06F13/362 , G06F13/37 , G06F13/378 , G06F9/46 , G06F15/16
CPC分类号： G06F13/37 , G06F13/378
摘要： In a data processing system, a bus is provided for the transfer of information between units coupled to the bus. The units are coupled in a priority arrangement which is distributed thereby providing priority logic in each of the units and allowing bus transfer cycles to be generated in an asynchronous manner. Priority is normally granted on the basis of physical position on the bus, highest priority being given to the first unit on the bus and lowest priority being given to the last unit on the bus. Each of the units includes priority logic which includes logic elements for requesting a bus cycle, such request being granted if no other higher priority unit has also requested a bus cycle. The request for and an indication of the grant of the bus cycle are stored in each unit so requesting and being granted the bus cycle respectively, only one such unit being capable of having the grant of a bus cycle at any given time, whereas any number of such units may have its request pending at any particular time. A modification to the priority logic allows a lowest priority unit to be physically positioned at other than the last unit position on the common bus.
摘要翻译：在数据处理系统中，提供总线用于在耦合到总线的单元之间传送信息。这些单元以分配的优先级布置耦合，从而在每个单元中提供优先级逻辑，并允许以异步方式生成总线传送周期。优先级通常基于总线上的物理位置授予，最高优先级被给予公共汽车上的第一单元，并且最低优先级被给予公共汽车上的最后一个单元。每个单元包括优先级逻辑，其包括用于请求总线周期的逻辑元件，如果没有其他较高优先级单元也请求了总线周期，则该请求被授权。总线周期的请求和授权指示被存储在每个单元中，从而请求并被分配给总线周期，只有一个这样的单元能够在任何给定的时间允许总线周期，而任何数量的这些单位可能会在任何特定的时间要求其请求。对优先级逻辑的修改允许最低优先级单元物理地定位在公共总线上的最后单元位置之外。

7. 发明授权

US4511959A Decentralized arbitration device for several processing units of a multiprocessor system 失效
标题翻译：多处理器系统的多个处理单元的分散仲裁设备
公开(公告)号：US4511959A
公开(公告)日：1985-04-16
申请号：US318136
申请日：1981-11-04
申请人： Alain Nicolas , Jean Chapelain
发明人： Alain Nicolas , Jean Chapelain
IPC分类号： G06F13/368 , G06F13/378 , G06F13/00
CPC分类号： G06F13/368 , G06F13/378
摘要： The decentralized arbitration device of the invention comprises an arbitration unit associated with each processing unit. This arbitration unit comprises an individual elementary arbitrator and a level elementary arbitrator. Their outputs are connected to a comparator which compares their output signals with the code of the unit considered, which code is supplied by a coding identification circuit. The individual priority request terminals of the units in the same level are connected together and the level priority request terminals of all the units are connected together.
摘要翻译：本发明的分散仲裁装置包括与每个处理单元相关联的仲裁单元。该仲裁单元包括单个初级仲裁器和级别初级仲裁器。它们的输出连接到比较器，比较器将其输出信号与所考虑单元的代码进行比较，该代码由编码识别电路提供。相同级别的单元的各个优先级请求终端连接在一起，并且所有单元的级别优先级请求终端连接在一起。

8. 发明授权

US4232366A Bus for a data processing system with overlapped sequences 失效
标题翻译：用于具有重叠序列的数据处理系统的总线
公开(公告)号：US4232366A
公开(公告)日：1980-11-04
申请号：US954601
申请日：1978-10-25
申请人： John V. Levy , David P. Rodgers , Robert E. Stewart , Richard J. Casabona
发明人： John V. Levy , David P. Rodgers , Robert E. Stewart , Richard J. Casabona
IPC分类号： G06F13/378 , G06F13/42 , G06F9/46
CPC分类号： G06F13/4217 , G06F13/378
摘要： A digital data processing system including an interconnection for the various elements that constitute the system. Each element that connects to the interconnection is called a nexus. For one element to communicate with another element, the one element, as a commanding nexus, seeks control of the interconnection and then transmits a command and address of a storage location in the other element when it receives control of the interconnection. Control is then relinquished unless the one element is to send data to the other element whereupon the data is sent immediately. If data is to be retrieved, the other element retrieves the data, requests control of the interconnection and, when it receives control, transmits the data onto the interconnection with an identification of the one element. The one element then retrieves the data from the interconnection when it recognizes its own identification. If the other element is a memory element, it also contains storage file for storing commands and data if it already is operating in response to another element's command.
摘要翻译：数字数据处理系统，包括构成系统的各种元件的互连。连接到互连的每个元件称为连接。为了与另一个元件通信的一个元件，作为命令关联的一个元件寻求对互连的控制，并且当它接收到互连的控制时，在另一元素中发送存储位置的命令和地址。然后放弃控制，除非一个元素要将数据发送到另一个元素，从而立即发送数据。如果要检索数据，则另一个元素检索数据，请求对互连的控制，并且当其接收到控制时，使用该元素的标识将数据发送到互连上。然后，一个元素在识别自己的标识时从互连中检索数据。如果另一个元素是内存元素，它还包含用于存储命令和数据的存储文件，如果它已经在响应另一个元素的命令而运行。

9. 发明申请

US20160179725A1 INPUT/OUTPUT METHOD IN VIRTUAL MACHINE ENVIRONMENTS 有权
标题翻译：虚拟机环境中的输入/输出方法
公开(公告)号：US20160179725A1
公开(公告)日：2016-06-23
申请号：US14976605
申请日：2015-12-21
申请人： Samsung Electronics Co., Ltd.
发明人： Sang-Geol Lee , Hyeon-Sang Eom , Heon-Young Yeom , Myoung-Won Oh
IPC分类号： G06F13/378 , G06F9/48 , G06F13/24 , G06F9/455
CPC分类号： G06F13/378 , G06F9/45545 , G06F9/45558 , G06F9/4812 , G06F13/24 , G06F2009/4557 , G06F2009/45579
摘要： A input/output method is disclosed for performing communications in a virtual machine (VM) environment between a host operating system (OS) and a guest OS. The input/output method includes performing request polling (RP) on an input/output event generated by a guest OS which is driven by a virtual machine (VM), sending an input/output request to a host OS, on which the VM runs. The input/output method further includes performing response waiting polling (RWP) on an input/output completion message generated by the host OS when the input/output event is detected through the RP, and sending an input/output response to the guest OS when the input/output completion message is detected through the RWP. In the method, the RP and the RWP are performed by multiple threads executed on the VM.
摘要翻译：公开了一种用于在主机操作系统（OS）和客户OS之间的虚拟机（VM）环境中执行通信的输入/输出方法。输入/输出方法包括对由虚拟机（VM）驱动的客户OS产生的输入/输出事件执行请求轮询（RP），向VM运行的主机OS发送输入/输出请求。输入/输出方法还包括当通过RP检测到输入/输出事件时，由主机OS产生的输入/输出完成消息执行响应等待轮询（RWP），以及当通过RP检测到输入/输出响应时，向客户操作系统发送输入/输出响应通过RWP检测输入/输出完成消息。在该方法中，RP和RWP由在VM上执行的多个线程执行。

10. 发明申请

US20070274117A1 RETRACTABLE CARD ADAPTER 有权
标题翻译：可回收卡适配器
公开(公告)号：US20070274117A1
公开(公告)日：2007-11-29
申请号：US11422313
申请日：2006-06-05
申请人： Jeffrey A. Salazar , Robert A. Howard , Jonathan R. Harris , Daren W. Hebold
发明人： Jeffrey A. Salazar , Robert A. Howard , Jonathan R. Harris , Daren W. Hebold
IPC分类号： G11C5/00
CPC分类号： H05K5/0278 , G06F13/378
摘要： Methods and apparatus for interfacing a memory device with a host device are 5 disclosed. According to one aspect of the present invention, an apparatus which enables a non-volatile memory device to communicate with a host device includes a body and an element. The body has a boundary, and the element is arranged to move at least partially within the body. The element includes an interface which may be coupled to the host device when the element is in a first position with respect to the body. The element is 10 also arranged to receive the non-volatile memory device and to move the non-volatile memory device and the interface with respect to the body. In one embodiment, when the element is in the first position with respect to the body, the interface at least partially extends past the boundary associated with the body.
摘要翻译：公开了用于将存储器设备与主机设备接口的方法和设备。根据本发明的一个方面，一种能够使非易失性存储装置与主机进行通信的装置包括主体和元件。身体具有边界，并且元件被布置成至少部分地移动到身体内。元件包括当元件相对于主体处于第一位置时可以耦合到主机设备的接口。该元件10还布置成接收非易失性存储器件并且相对于身体移动非易失性存储器件和界面。在一个实施例中，当元件相对于主体处于第一位置时，界面至少部分延伸超过与主体相关联的边界。

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