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1. 发明申请

US20160179725A1 INPUT/OUTPUT METHOD IN VIRTUAL MACHINE ENVIRONMENTS 有权
标题翻译：虚拟机环境中的输入/输出方法
公开(公告)号：US20160179725A1
公开(公告)日：2016-06-23
申请号：US14976605
申请日：2015-12-21
申请人： Samsung Electronics Co., Ltd.
发明人： Sang-Geol Lee , Hyeon-Sang Eom , Heon-Young Yeom , Myoung-Won Oh
IPC分类号： G06F13/378 , G06F9/48 , G06F13/24 , G06F9/455
CPC分类号： G06F13/378 , G06F9/45545 , G06F9/45558 , G06F9/4812 , G06F13/24 , G06F2009/4557 , G06F2009/45579
摘要： A input/output method is disclosed for performing communications in a virtual machine (VM) environment between a host operating system (OS) and a guest OS. The input/output method includes performing request polling (RP) on an input/output event generated by a guest OS which is driven by a virtual machine (VM), sending an input/output request to a host OS, on which the VM runs. The input/output method further includes performing response waiting polling (RWP) on an input/output completion message generated by the host OS when the input/output event is detected through the RP, and sending an input/output response to the guest OS when the input/output completion message is detected through the RWP. In the method, the RP and the RWP are performed by multiple threads executed on the VM.
摘要翻译：公开了一种用于在主机操作系统（OS）和客户OS之间的虚拟机（VM）环境中执行通信的输入/输出方法。输入/输出方法包括对由虚拟机（VM）驱动的客户OS产生的输入/输出事件执行请求轮询（RP），向VM运行的主机OS发送输入/输出请求。输入/输出方法还包括当通过RP检测到输入/输出事件时，由主机OS产生的输入/输出完成消息执行响应等待轮询（RWP），以及当通过RP检测到输入/输出响应时，向客户操作系统发送输入/输出响应通过RWP检测输入/输出完成消息。在该方法中，RP和RWP由在VM上执行的多个线程执行。

2. 发明授权

US5761451A Configuration with several active and passive bus users 失效
标题翻译：配置多个主动和被动总线用户
公开(公告)号：US5761451A
公开(公告)日：1998-06-02
申请号：US433397
申请日：1995-05-04
申请人： Michael Abert , Siegfried Block , Johannes Bozenhardt , Franz Leigsnering , Werner Pfatteicher , Franz-Clemens Schewe
发明人： Michael Abert , Siegfried Block , Johannes Bozenhardt , Franz Leigsnering , Werner Pfatteicher , Franz-Clemens Schewe
IPC分类号： G06F13/18 , G06F13/16 , G06F13/368 , G06F13/378 , H01J13/00
CPC分类号： G06F13/378 , G06F13/1652 , G06F13/368
摘要： A system having several active (master) and passive (slave) bus users (processors), each of which is allocated a memory with its own memory area. Each bus user has read access to its own memory area and each active (master) bus user has write access to every memory area. A control line is provided for sending a control signal which indicates to the active (master) bus users accessing the memory areas whether data have already been written into the memory areas. The control signal has dominant and recessive states. Outside of the access cycles, all bus users generate a dominant state. During a cycle of access to memory areas, only the bus users in whose memory areas the data have not yet been written, generate such a signal. The system may be used in automation systems.
摘要翻译： PCT No.PCT / DE93 / 01042 Sec。 371日期：1995年5月4日 102（e）日期1995年5月4日PCT提交1993年10月29日PCT公布。公开号WO94 / 10632 日期1994年5月11日具有几个主（主）和无源（从））总线用户（处理器）的系统，其中每个被分配有具有其自己的存储区的存储器。每个总线用户具有对其自己的存储区域的读取访问权限，并且每个活动（主）总线用户具有对每个存储器区域的写入访问。提供控制线，用于发送控制信号，该控制信号指示对存储区域的有效（主）总线用户是否已经将数据写入存储区域。控制信号具有显性和隐性状态。在访问周期之外，所有总线用户都产生主导状态。在访问存储器区域的周期期间，只有其存储区域中的数据尚未被写入的总线用户才产生这样的信号。该系统可用于自动化系统。

3. 发明授权

US5034881A Method of and system for controlling common bus 失效
标题翻译：普通总线控制方法及系统
公开(公告)号：US5034881A
公开(公告)日：1991-07-23
申请号：US340476
申请日：1989-04-19
申请人： Kouichi Hoashi , Noriaki Uchida
发明人： Kouichi Hoashi , Noriaki Uchida
IPC分类号： G06F13/362 , G06F13/378
CPC分类号： G06F13/378
摘要： In a common bus control method of a distributed arbitration in which a contention between bus usage requests from a plurality of units connected to a common bus is arbitrated by each unit by use of an identifier representing a priority level and assigned thereto, unit identifiers are dynamically exchanged between a unit having a highest priority level and a unit having a lower priority level, thereby enabling the respective units to use the common bus at a balanced usage frequency.
摘要翻译：在分布式仲裁的公共总线控制方法中，通过使用表示优先级的标识符分配给每个单元来对来自连接到公共总线的多个单元的总线使用请求之间的争用进行仲裁，单元标识符是动态的在具有最高优先级的单元和具有较低优先级的单元之间交换，从而使各个单元能够以平衡的使用频率使用公共总线。

4. 发明授权

US4745548A Decentralized bus arbitration using distributed arbiters having circuitry for latching lockout signals gated from higher priority arbiters 失效
标题翻译：使用具有用于锁存从较高优先权仲裁器门控的锁定信号的电路的分布式仲裁器进行分散总线仲裁
公开(公告)号：US4745548A
公开(公告)日：1988-05-17
申请号：US9634
申请日：1987-01-23
申请人： Donald E. Blahut
发明人： Donald E. Blahut
IPC分类号： G06F13/378 , G06F13/00 , G06F13/18 , G06F13/26 , G06F13/36
CPC分类号： G06F13/378
摘要： A silicon semiconductor wafer containing a plurality of silicon integrated circuits formed therein or attached thereto contains at least one data bus to which some of the circuits are connected. Each of the circuits coupled to the data bus contains an arbitration request circuit which selectively passes a signal that requests that its circuit be given access to the data bus so it can transmit information to another circuit on the wafer. In addition, each of the circuits coupled to the data bus has an arbitration circuit which detects which of any of the circuits coupled to the data bus is requesting access to the data bus and facilitates its circuit gaining access to the data bus if its circuit has a higher preselected priority than any other circuit which is simultaneously seeking access to the data bus. The distribution of the arbitration request circuits and of the arbitration circuits simplifies layout and tends to improve the speed of operation.
摘要翻译：包含形成在其中或附着于其上的多个硅集成电路的硅半导体晶片包含至少一个数据总线，一些电路连接到该数据总线。耦合到数据总线的每个电路包含仲裁请求电路，该电路选择性地传递请求其电路被给予数据总线的信号，以便它可以向晶片上的另一个电路发送信息。另外，耦合到数据总线的每个电路具有仲裁电路，其检测耦合到数据总线的任何电路中的哪一个请求访问数据总线，并且如果其电路具有数据总线，则有助于其电路访问数据总线比同时寻求访问数据总线的任何其他电路更高的预选优先级。仲裁请求电路和仲裁电路的分布简化了布局，并且倾向于提高操作速度。

5. 发明授权

US4641237A Bus control method and apparatus 失效
标题翻译：总线控制方法和装置
公开(公告)号：US4641237A
公开(公告)日：1987-02-03
申请号：US530078
申请日：1983-09-07
申请人： Masaharu Yabushita , Makoto Nohmi , Nobuyuki Fujikura , Shoji Miyamoto , Hirokazu Ihara
发明人： Masaharu Yabushita , Makoto Nohmi , Nobuyuki Fujikura , Shoji Miyamoto , Hirokazu Ihara
IPC分类号： G06F13/36 , G06F13/378 , G06F13/38 , G06F13/40 , G06F15/173 , G06F15/80 , G06F13/14
CPC分类号： G06F13/378 , G06F13/4022 , G06F15/17343 , G06F15/80
摘要： A bus control method and apparatus wherein buses each coupling a pair of processors are serially arranged rectilinearly into a cluster bus which is arranged in one direction and wherein a plurality of such cluster buses are arranged in a plurality of directions as a lattice pattern to form a multiprocessor system. Each of the processors supplies the respective cluster buses with send request and priority processing level signals and receives a receipt acknowledge signal from another processor on the same cluster bus, thereby to occupy said cluster bus, so as to transfer data to the other processor on the cluster bus.
摘要翻译：一种总线控制方法和装置，其中连接一对处理器的总线被直线地串行布置成沿一个方向布置的集群总线，并且其中多个这样的集群总线以多个方向布置为格子图案，以形成多处理器系统每个处理器向相应的集群总线提供发送请求和优先级处理级信号，并从相同集群总线上的另一个处理器接收接收确认信号，从而占用所述集群总线，以便将数据传输到另一个处理器集群总线。

6. 发明授权

US4608700A Serial multi-drop data link 失效
标题翻译：串行多点数据链接
公开(公告)号：US4608700A
公开(公告)日：1986-08-26
申请号：US417763
申请日：1982-07-29
申请人： James L. Kirtley, Jr. , Thomas L. Sterling , Ronald D. Williams
发明人： James L. Kirtley, Jr. , Thomas L. Sterling , Ronald D. Williams
IPC分类号： G06F13/368 , G06F13/378 , G06F13/42 , H04L12/417 , H04B3/00
CPC分类号： H04L12/417 , G06F13/368 , G06F13/378 , G06F13/4213
摘要： A digital data link for communication between distributed components including at least two serial paths, a data path and a control path, and a port associated with each component, the ports serving to arbitrate link access requests, permit dialog with minimal addressing between components and promote effective utilization of the data path bandwidth.
摘要翻译： PCT No.PCT / US81 / 00986 Sec。 371日期1982年7月29日 102（e）1982年7月29日PCT PCT。1981年7月23日提交。一种用于在分布式组件之间进行通信的数字数据链路，包括至少两个串行路径，数据路径和控制路径以及与每个组件相关联的端口，用于仲裁链接访问请求的端口允许在组件之间进行最小寻址的对话，并促进数据路径带宽的有效利用。

7. 发明授权

US4433375A System for superposition of the successive stages of the transfer of data among several data processing units 失效
标题翻译：在几个数据处理单位之间监督数据传输的后续阶段的系统
公开(公告)号：US4433375A
公开(公告)日：1984-02-21
申请号：US210359
申请日：1980-11-25
申请人： Daniel R. Vinot
发明人： Daniel R. Vinot
IPC分类号： G06F9/46 , G06F13/362 , G06F13/378 , G06F13/42 , G06F15/16 , G06F15/177 , G06F7/00
CPC分类号： G06F13/378 , G06F13/4217
摘要： A control logic circuit (C) is provided in each unit such as processors and memories in a multiple processor data processing system. Each control logic circuit (C) is equipped with a priority circuit (P12) which at one input receives the eligible local calls (RQ.sub.i L) of the unit itself and at the other input receives external calls (RQ.sub.k) transmitted by the other units. The control logic circuit (C) enables control by its unit of a transmission bus only when its priority circuit (P12) recognizes that unit as having the highest priority among the other units. The logic circuit (C) together with a T circuit (13) selects local calls as a function of the state of occupation of the data lines of the transmission bus.
摘要翻译：在多处理器数据处理系统中的每个单元中提供控制逻辑电路（C），例如处理器和存储器。每个控制逻辑电路（C）配备有一个优先级电路（P12），在一个输入端接收单元本身的合格本地呼叫（RQiL），另一个输入接收由其他单元发送的外部呼叫（RQk）。控制逻辑电路（C）能够通过其传输单元进行控制，但只有当其优先级电路（P12）将该单元识别为具有最高优先级的其他单元时才能进行控制。逻辑电路（C）与T电路（13）一起根据传输总线的数据线的占用状态选择本地呼叫。

8. 发明授权

US4290133A System timing means for data processing system 失效
标题翻译：数据处理系统的系统定时手段
公开(公告)号：US4290133A
公开(公告)日：1981-09-15
申请号：US954604
申请日：1978-10-25
申请人： Robert E. Stewart , Barry J. Flahive , David Potter
发明人： Robert E. Stewart , Barry J. Flahive , David Potter
IPC分类号： G06F13/378 , G06F13/42 , H04J3/08
CPC分类号： G06F13/378 , G06F13/4217
摘要： A digital data processing system including an interconnection for the various elements that constitute the system. Each element that connects to the interconnection is called a nexus, and each nexus in the system can communicate with other nexuses. A central clocking circuit generates timing signals that control such communications on a synchronous basis. The clocking circuit includes oscillator, control and sequencing circuits that produce phase and clocking signals that are coupled to each nexus. Each nexus contains receivers and decoders for converting the phase and clocking signals into a sequence of internal timing signals that synchronizes the operation of the nexus to transfers among the nexuses.
摘要翻译：数字数据处理系统，包括构成系统的各种元件的互连。连接到互连的每个元素称为连接，系统中的每个连接可以与其他的nexus通信。中央时钟电路产生在同步基础上控制这种通信的定时信号。时钟电路包括振荡器，控制和排序电路，其产生耦合到每个连接点的相位和时钟信号。每个连接器包含用于将相位和时钟信号转换成内部定时信号的序列的接收器和解码器，其将该连接的操作与该互连之间的传输同步。

9. 发明授权

US09996488B2 I3C high data rate (HDR) always-on image sensor 8-bit operation indicator and buffer over threshold indicator 有权
公开(公告)号：US09996488B2
公开(公告)日：2018-06-12
申请号：US15246098
申请日：2016-08-24
申请人： QUALCOMM Incorporated
发明人： Shoichiro Sengoku
IPC分类号： G06F13/00 , G06F13/364 , G06F13/16 , G06F13/42 , G06F13/24 , G06F13/378 , G06F13/362
CPC分类号： G06F13/364 , G06F13/1673 , G06F13/24 , G06F13/362 , G06F13/378 , G06F13/4282
摘要： A method for enabling 8-bit data word access over a protocol limited to 16-bit data word access is provided. Data may be encapsulated within the lowest 19 bits of a 20-bit number. If it is ascertained that an 8-bit data word is to be used in a system supporting only 16-bit data word access, a byte-enable indicator may be provided within a most significant bit of the 20-bit number while also allocating an 8-bit data region for transfer of the 8-bit data word. The 20-bit number may then be transcoded into a 12-digit ternary number, wherein a residual numerical region is defined as a number space by which a first numerical region defined for the 12-digit ternary number exceeds a second numerical region defined by the lowest 19 bits of the 20-bit number.

10. 发明授权

US09690487B2 Storage apparatus and method for controlling storage apparatus 有权
公开(公告)号：US09690487B2
公开(公告)日：2017-06-27
申请号：US14790861
申请日：2015-07-02
申请人： HITACHI, LTD. , Hitachi Information & Telecommunication Engineering Ltd.
发明人： Mitsuo Hayasaka , Koji Yamasaki
IPC分类号： G06F7/53 , G06F13/378 , G06F13/20 , G06F3/06 , G06F17/30
CPC分类号： G06F3/0608 , G06F3/0619 , G06F3/0641 , G06F3/065 , G06F3/067 , G06F17/30156
摘要： Upon receipt of an I/O request instructing storage of data in a storage device 106 from a host apparatus, a storage apparatus 100 selects a de-duplication process method to be applied to the received data, based on at least any of influence on processing performance of the storage apparatus 100 to be performed by execution of a first de-duplication process method (inline method) in which the de-duplication process is performed on the data immediately after the receipt of the I/O request, influence on the processing performance of the storage apparatus 100 to be performed by execution of a second de-duplication process method (post-process method) in which the de-duplication process is performed on the data at later timing, and the size of a temporary storage device 106b to be required for the processing of the data by the second de-duplication process method.

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