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81. 发明申请

US20120099622A1 REPEATER CIRCUIT WITH MULTIPLEXER AND STATE ELEMENT FUNCTIONALITY 有权
标题翻译：具有多路复用器和状态元件功能的重复电路
公开(公告)号：US20120099622A1
公开(公告)日：2012-04-26
申请号：US12908167
申请日：2010-10-20
申请人： Robert P. Masleid , Anand Dixit
发明人： Robert P. Masleid , Anand Dixit
IPC分类号： H03H11/26 , H04B3/36
CPC分类号： H04B3/36 , H03K3/356008 , H03K17/693
摘要： A circuit implementing multiplexer, storage, and repeater functions is disclosed. The circuit includes first and second input stages having first and second data inputs, respectively. An output stage is configured to drive an output signal. The first input stage is configured to activate the output stage responsive to a first condition, while the second input stage is configured to activate the output stage responsive to a second condition. An intermediate stage is configured to deactivate the output stage at a first delay time subsequent to one of the first or second input stages activating the output stage. The repeater circuit also includes a storage element configured to store a state of the output signal, and further configured to cause the output node to be held at the state of the output signal subsequent to deactivation of the output stage.
摘要翻译：公开了实现多路复用器，存储和转发器功能的电路。电路包括分别具有第一和第二数据输入的第一和第二输入级。输出级被配置为驱动输出信号。第一输入级被配置为响应于第一状态激活输出级，而第二输入级被配置为响应于第二状态激活输出级。中间级被配置为在第一或第二输入级中的一个激活输出级之后的第一延迟时间停用输出级。中继器电路还包括存储元件，其被配置为存储输出信号的状态，并且还被配置为使输出节点在输出级的去激活之后保持在输出信号的状态。

82. 发明申请

US20110072326A1 SRAM MACRO TEST FLOP 有权
标题翻译： SRAM宏测试平台
公开(公告)号：US20110072326A1
公开(公告)日：2011-03-24
申请号：US12565689
申请日：2009-09-23
申请人： Ali Vahidsafa , Robert P. Masleid , Jason M. Hart , Zhirong Feng
发明人： Ali Vahidsafa , Robert P. Masleid , Jason M. Hart , Zhirong Feng
IPC分类号： G06F11/00 , G06F12/00
CPC分类号： G01R31/318541 , G11C11/41 , G11C29/003 , G11C29/22 , G11C29/32 , G11C29/48
摘要： A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master feed-back circuit including a master storage node and a master feed-forward circuit. The slave latch circuit includes a slave feed-back circuit including a slave storage node and a slave feed-forward circuit driven from the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit comprising a scan storage node and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from master latch circuit and a slave driver driven from slave latch circuit.
摘要翻译： SRAM（静态随机存取存储器）宏测试电路包括触发电路，扫描控制电路和输出缓冲电路。触发器电路包括主锁存电路和从锁存电路。主锁存电路包括主反馈电路，主电路包括主存储节点和主前馈电路。从锁存电路包括从主存储节点和从主锁存器驱动的从前馈电路的从属反馈电路。扫描控制电路包括扫描从机前馈电路，扫描锁存电路和由扫描反馈电路驱动的扫描驱动电路。扫描锁存电路包括扫描反馈电路，其包括从从锁存器驱动的扫描存储节点和扫描前馈电路。输出缓冲电路包括从主锁存电路驱动的主驱动器和从从锁存电路驱动的从驱动器。

83. 发明申请

US20100264973A1 ECONOMY PRECISION PULSE GENERATOR 有权
标题翻译：经济精密脉冲发生器
公开(公告)号：US20100264973A1
公开(公告)日：2010-10-21
申请号：US12425176
申请日：2009-04-16
申请人： Robert P. Masleid , David J. Greenhill , Bijoy Kalloor
发明人： Robert P. Masleid , David J. Greenhill , Bijoy Kalloor
IPC分类号： G06F1/04
CPC分类号： H03K3/355
摘要： A system includes an input device, an output device, a mechanical chassis, a printed circuit board, and a semiconductor device. The semiconductor device includes a mechanical package, and a semiconductor die. The semiconductor die includes a semiconductor layer, a plurality of metal layers, a clock distribution network that distributes a clock signal within the die, and an economy precision pulse generating circuit. The economy precision pulse generating circuit includes a pre-charge circuit, a gate-to-the-partial-jam-latch-keeper circuit, a partial-jam-latch-keeper circuit, and a pull-down-against-the-up-keeper circuit. A source clock signal is derived from the clock signal. The source clock signal is provided to a first input of a logical AND circuit, the pre-charge circuit, and the gate-to-the-partial-jam-latch-keeper circuit. A common storage node is connected to a second input of the logical AND circuit. The logical AND circuit outputs an output pulse. The output pulse is fed back to the pull-down-against-the-up-keeper circuit.
摘要翻译：系统包括输入装置，输出装置，机械底盘，印刷电路板和半导体装置。半导体器件包括机械封装和半导体管芯。半导体管芯包括半导体层，多个金属层，在管芯内分布时钟信号的时钟分配网络和经济精密脉冲发生电路。经济精密脉冲发生电路包括预充电电路，门到部分卡锁锁存器电路，部分卡锁锁存器电路，以及下拉向上守门员电路。源时钟信号从时钟信号导出。源时钟信号被提供给逻辑与电路的第一输入，预充电电路以及门到部分卡锁锁存器电路。公共存储节点连接到逻辑与电路的第二输入。逻辑“与”电路输出一个输出脉冲。输出脉冲反馈到下拉向上保持电路。

84. 发明授权

US07791393B1 Precision falling edge generator 有权
标题翻译：精密下降发生器
公开(公告)号：US07791393B1
公开(公告)日：2010-09-07
申请号：US12420540
申请日：2009-04-08
申请人： Robert P. Masleid , Heechoul Park , Jason M. Hart
发明人： Robert P. Masleid , Heechoul Park , Jason M. Hart
IPC分类号： H03K3/00
CPC分类号： H03K5/1506 , G06F1/10 , H03K5/151 , H03K5/1515
摘要： A clock generating circuit includes a source clock, a first clock generated from the source clock through a first header, a second clock generated from the source clock through a second header and an inverter, wherein the second clock is out of phase with respect to the first clock, a first delayed falling edge clock, wherein the first delayed falling edge clock corresponds to the first clock with a first delayed falling edge, and a second delayed falling edge clock, wherein the second delayed falling edge clock corresponds to the second clock with a second delayed falling edge. The first delayed falling edge clock is generated from a first leading edge path and a first falling edge path, both originating from the source clock, that are inputted to a first delay chain.
摘要翻译：时钟产生电路包括源时钟，通过第一标头从源时钟产生的第一时钟，通过第二标头从源时钟产生的第二时钟和反相器，其中第二时钟相对于第一时钟，第一延迟下降沿时钟，其中第一延迟下降沿时钟对应于具有第一延迟下降沿的第一时钟和第二延迟下降沿时钟，其中第二延迟下降沿时钟对应于第二时钟，第二个延迟下降。第一延迟下降沿时钟从被输入到第一延迟链的源极时钟的第一前沿路径和第一下降沿路径生成。

85. 发明授权

US07777523B1 Level shifter flip-flop 有权
标题翻译：电平移位器触发器
公开(公告)号：US07777523B1
公开(公告)日：2010-08-17
申请号：US12359933
申请日：2009-01-26
申请人： Robert P. Masleid , Jason M. Hart
发明人： Robert P. Masleid , Jason M. Hart
IPC分类号： H03K19/094
CPC分类号： H03K3/356139 , H03K3/35625
摘要： A flip-flop or other state circuit that includes level-shifting functionality. In connection with a flip-flop, embodiments include an inverter circuit element that has a data input line as its input and a data complement line as its output. The inverter resides in voltage domain that is lower than the voltage domain associated with remainder of the flip-flop.
摘要翻译：包括电平转换功能的触发器或其他状态电路。结合触发器，实施例包括具有作为其输入的数据输入线和作为其输出的数据互补线的逆变器电路元件。逆变器的电压域低于与触发器的剩余部分相关联的电压域。

86. 发明申请

US20100188130A1 LOW RC LOCAL CLOCK DISTRIBUTION 有权
标题翻译：低RC本地时钟分配
公开(公告)号：US20100188130A1
公开(公告)日：2010-07-29
申请号：US12361027
申请日：2009-01-28
申请人： Robert P. Masleid
发明人： Robert P. Masleid
IPC分类号： H03K3/00
CPC分类号： G06F1/10
摘要： A system includes an input device, an output device, a printed circuit board, and a semiconductor device. The semiconductor device includes a semiconductor die. The semiconductor die includes a clock distribution network that distributes a primary clock signal. The clock distribution network includes a low RC local clock distribution structure. The low RC local clock distribution structure includes a conductor, a first clock signal incident on the conductor, a local gain buffer pair that receives the first clock signal and outputs a second clock signal corresponding to the first clock signal, and a shorting bar that shorts the second clock signal to a plurality of conductors.
摘要翻译：一种系统包括输入装置，输出装置，印刷电路板和半导体装置。半导体器件包括半导体管芯。半导体管芯包括分配主时钟信号的时钟分配网络。时钟分配网络包括一个低RC本地时钟分配结构。低RC本地时钟分配结构包括导体，入射在导体上的第一时钟信号，接收第一时钟信号并输出对应于第一时钟信号的第二时钟信号的局部增益缓冲器对，以及短路的短路第二时钟信号到多个导体。

87. 发明申请

US20100164578A1 REPEATER CIRCUIT WITH STAGED OUTPUT 有权
标题翻译：具有分布输出的重复电路
公开(公告)号：US20100164578A1
公开(公告)日：2010-07-01
申请号：US12345036
申请日：2008-12-29
申请人： Robert P. Masleid
发明人： Robert P. Masleid
IPC分类号： H03K5/00
CPC分类号： H03K3/012 , H03K3/356113 , H03K3/356165
摘要： A repeater circuit. The repeater circuit includes a first output stage having two output circuits, a second output stage having two additional output circuits, two activation circuits, and two deactivation circuits. Responsive to detecting a logical transition of an input signal, one of the activation circuits is configured to activate a corresponding output circuit, and responsive thereto another corresponding output circuit is configured to be activated. The output circuits drive an output signal on the output node. A corresponding one of the deactivation circuits is configured to deactivate the corresponding output circuit after a delay time has elapsed, whereas the other corresponding output circuit is deactivated in response thereto. A keeper circuit is configured to continue providing the output signal on the output node after deactivation of the corresponding output circuits.
摘要翻译：中继器电路。中继器电路包括具有两个输出电路的第一输出级，具有两个附加输出电路的第二输出级，两个激活电路和两个去激活电路。响应于检测输入信号的逻辑转换，激活电路之一被配置为激活对应的输出电路，并且响应于另一个相应的输出电路被配置为被激活。输出电路驱动输出节点上的输出信号。停用电路中的相应一个被配置为在延迟时间过去之后停用相应的输出电路，而响应于另一个对应的输出电路被去激活。保持器电路被配置为在对应的输出电路去激活之后在输出节点上继续提供输出信号。

88. 发明申请

US20100164557A1 ACTIVE ECHO ON-DIE REPEATER CIRCUIT 有权
标题翻译：主动式ECHO电源插座电路
公开(公告)号：US20100164557A1
公开(公告)日：2010-07-01
申请号：US12345009
申请日：2008-12-29
申请人： Robert P. Masleid , Ilyas Elkin
发明人： Robert P. Masleid , Ilyas Elkin
IPC分类号： H03B1/00
CPC分类号： H04B3/36 , H04B3/23 , H04L25/20
摘要： A repeater circuit. The repeater circuit includes two output circuits, two echo circuits, two activation circuits, and two deactivation circuits. Responsive to detecting a logical transition of an input signal, one of the activation circuits is configured to activate a corresponding output circuit, which is configured to drive an output signal on an output node. A corresponding echo circuit is configured to be activated and to drive an input node responsive to activation of the corresponding output circuit. A corresponding one of the deactivation circuits is configured to deactivate the corresponding output circuit after a delay time has elapsed, whereas the corresponding echo circuit is deactivated in response thereto. A keeper circuit is configured to continue providing the output signal on the output node after deactivation of the corresponding output circuit.
摘要翻译：中继器电路。中继器电路包括两个输出电路，两个回波电路，两个激活电路和两个去激活电路。响应于检测输入信号的逻辑转换，激活电路之一被配置为激活相应的输出电路，其被配置为驱动输出节点上的输出信号。相应的回波电路被配置为被激活并且响应于对应的输出电路的激活来驱动输入节点。停用电路中的相应一个被配置为在延迟时间过去之后去激活相应的输出电路，而对应的回波电路则响应于此停用。保持器电路被配置为在对应的输出电路去激活之后继续在输出节点上提供输出信号。

89. 发明申请

US20100156504A1 CROSS POINT SWITCH 有权
标题翻译：交叉点开关
公开(公告)号：US20100156504A1
公开(公告)日：2010-06-24
申请号：US12715105
申请日：2010-03-01
申请人： Robert P. Masleid , Scott Pitkethly
发明人： Robert P. Masleid , Scott Pitkethly
IPC分类号： H03K17/62
CPC分类号： H03K19/09429 , H03K17/002
摘要： A cross point switch, in accordance with one embodiment of the present invention, includes a plurality of tri-state repeaters coupled to form a plurality of multiplexers. Each set of corresponding tri-state repeaters in the plurality of multiplexers share a front end module such that delay through the cross point switch due to input capacitance is reduced as compared to conventional cross point switches.
摘要翻译：根据本发明的一个实施例的交叉点开关包括耦合以形成多个多路复用器的多个三态中继器。多个多路复用器中的每组相应的三态中继器共享前端模块，使得与传统的交叉点开关相比，由于输入电容而导致的交叉点开关的延迟减小。

90. 发明授权

US07725656B1 Braided set associative caching techniques 有权
标题翻译：编织组合缓存技术
公开(公告)号：US07725656B1
公开(公告)日：2010-05-25
申请号：US11583463
申请日：2006-10-18
申请人： Guillermo Rozas , Alexander Klaiber , Robert P. Masleid , John Banning , James Van Zoeren , Paul Serris
发明人： Guillermo Rozas , Alexander Klaiber , Robert P. Masleid , John Banning , James Van Zoeren , Paul Serris
IPC分类号： G06F13/00
CPC分类号： G06F12/0864
摘要： A method and apparatus for storing and retrieving data in an N-way set associative cache with N data array banks is disclosed. On a cache fill corresponding to a particular way, a portion of each cache line (called a chunk) is placed in each data array bank. On a processor load seeking a requested chunk, a candidate chunk is retrieved from each data array bank and the requested chunk is selected from among the candidates.
摘要翻译：公开了一种用于在具有N个数据阵列组的N路组合关联高速缓存中存储和检索数据的方法和装置。在对应于特定方式的缓存填充中，每个高速缓存行（称为块）的一部分被放置在每个数据阵列组中。在寻求所请求的块的处理器负载上，从每个数据阵列库中检索候选块，并且从候选中选择所请求的块。

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