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1. 发明授权

US07592836B1 Multi-write memory circuit with multiple data inputs 有权
标题翻译：具有多个数据输入的多写存储器电路
公开(公告)号：US07592836B1
公开(公告)日：2009-09-22
申请号：US11396114
申请日：2006-03-31
申请人： Robert P. Masleid , Scott Pitkethly
发明人： Robert P. Masleid , Scott Pitkethly
IPC分类号： G06F7/38 , H03K19/173 , H03K3/00 , G11C11/00
CPC分类号： G11C11/412 , H03K5/135
摘要： Various types of memory circuits are described. A memory circuit may include a state-storage feedback loop coupled to a first data input and to a second data input. The first data input is introduced into the feedback loop at a first set of points, and the second data input is introduced into the feedback loop at a second set of points.
摘要翻译：描述各种类型的存储器电路。存储器电路可以包括耦合到第一数据输入和第二数据输入的状态存储反馈回路。第一数据输入在第一组点被引入到反馈回路中，并且第二数据输入在第二组点被引入到反馈回路中。

2. 发明授权

US07872492B2 Triple latch flip flop system and method 失效
标题翻译：三重锁存触发器系统和方法
公开(公告)号：US07872492B2
公开(公告)日：2011-01-18
申请号：US12391993
申请日：2009-02-24
申请人： Scott Pitkethly , Robert P. Masleid
发明人： Scott Pitkethly , Robert P. Masleid
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K3/356191 , H03K3/012 , H03K17/162 , H03K17/6872
摘要： A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down node. The primary latch records state of the triple latch flip-flop system. The output for outputting a logic value based upon outputs of the pull up latch, pull down latch and the primary latch.
摘要翻译：公开了三重锁存触发器系统和方法。在一个实施例中，三重锁存触发器系统包括上拉锁存器，下拉锁存器，主锁存器和输出端。上拉闩锁驱动一个上拉节点。下拉锁存器驱动下拉节点。主锁存器记录三重锁存触发器系统的状态。用于根据上拉锁存器，下拉锁存器和主锁存器的输出输出逻辑值的输出。

3. 发明授权

US07710153B1 Cross point switch 有权
标题翻译：交叉开关
公开(公告)号：US07710153B1
公开(公告)日：2010-05-04
申请号：US11479618
申请日：2006-06-30
申请人： Robert P. Masleid , Scott Pitkethly
发明人： Robert P. Masleid , Scott Pitkethly
IPC分类号： H03K19/094
CPC分类号： H03K19/09429 , H03K17/002
摘要： A cross point switch, in accordance with one embodiment of the present invention, includes a plurality of tri-state repeaters coupled to form a plurality of multiplexers. Each set of corresponding tri-state repeaters in the plurality of multiplexers share a front end module such that delay through the cross point switch due to input capacitance is reduced as compared to conventional cross point switches.
摘要翻译：根据本发明的一个实施例的交叉点开关包括耦合以形成多个多路复用器的多个三态中继器。多个多路复用器中的每组相应的三态中继器共享前端模块，使得与传统的交叉点开关相比，由于输入电容而导致的交叉点开关的延迟减小。

4. 发明授权

US07689963B1 Double diamond clock and power distribution 有权
标题翻译：双金刚石时钟和配电
公开(公告)号：US07689963B1
公开(公告)日：2010-03-30
申请号：US11477970
申请日：2006-06-28
申请人： Robert P. Masleid , Scott Pitkethly
发明人： Robert P. Masleid , Scott Pitkethly
IPC分类号： G06F17/50 , H03K3/00 , H01L21/82
CPC分类号： G06F1/10
摘要： Systems and methods of double diamond clock and power distribution. In accordance with a first embodiment of the present invention, an integrated circuit comprises a first metallization layer. that is substantially a power plane and a second metallization layer disposed immediately adjacent to the first metallization layer. The first metallization layer and the second metallization layer are separated by an inter-plane distance. A signal trace on the first metallization layer is separated from the power plane by about three times the inter-plane distance.
摘要翻译：双金刚石时钟和配电系统及方法。根据本发明的第一实施例，集成电路包括第一金属化层。其基本上是与第一金属化层紧邻设置的电源平面和第二金属化层。第一金属化层和第二金属化层由平面间距离分开。第一金属化层上的信号迹线与电源平面分开约三倍的平面间距离。

5. 发明授权

US09178505B2 Cross point switch 有权
标题翻译：交叉开关
公开(公告)号：US09178505B2
公开(公告)日：2015-11-03
申请号：US12715105
申请日：2010-03-01
申请人： Robert P. Masleid , Scott Pitkethly
发明人： Robert P. Masleid , Scott Pitkethly
IPC分类号： H03K19/094 , H03K17/00
CPC分类号： H03K19/09429 , H03K17/002
摘要： A cross point switch, in accordance with one embodiment of the present invention, includes a plurality of tri-state repeaters coupled to form a plurality of multiplexers. Each set of corresponding tri-state repeaters in the plurality of multiplexers share a front end module such that delay through the cross point switch due to input capacitance is reduced as compared to conventional cross point switches.
摘要翻译：根据本发明的一个实施例的交叉点开关包括耦合以形成多个多路复用器的多个三态中继器。多个多路复用器中的每组相应的三态中继器共享前端模块，使得与传统的交叉点开关相比，由于输入电容而导致的交叉点开关的延迟减小。

6. 发明申请

US20090212815A1 TRIPLE LATCH FLIP FLOP SYSTEM AND METHOD 失效
标题翻译：三叶式襟翼浮雕系统及方法
公开(公告)号：US20090212815A1
公开(公告)日：2009-08-27
申请号：US12391993
申请日：2009-02-24
申请人： Scott Pitkethly , Robert P. Masleid
发明人： Scott Pitkethly , Robert P. Masleid
IPC分类号： H03K17/16
CPC分类号： H03K3/356191 , H03K3/012 , H03K17/162 , H03K17/6872
摘要： A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down node. The primary latch records state of the triple latch flip-flop system. The output for outputting a logic value based upon outputs of the pull up latch, pull down latch and the primary latch.
摘要翻译：公开了三重锁存触发器系统和方法。在一个实施例中，三重锁存触发器系统包括上拉锁存器，下拉锁存器，主锁存器和输出端。上拉闩锁驱动一个上拉节点。下拉锁存器驱动下拉节点。主锁存器记录三重锁存触发器系统的状态。用于根据上拉锁存器，下拉锁存器和主锁存器的输出输出逻辑值的输出。

7. 发明申请

US20100156504A1 CROSS POINT SWITCH 有权
标题翻译：交叉点开关
公开(公告)号：US20100156504A1
公开(公告)日：2010-06-24
申请号：US12715105
申请日：2010-03-01
申请人： Robert P. Masleid , Scott Pitkethly
发明人： Robert P. Masleid , Scott Pitkethly
IPC分类号： H03K17/62
CPC分类号： H03K19/09429 , H03K17/002
摘要： A cross point switch, in accordance with one embodiment of the present invention, includes a plurality of tri-state repeaters coupled to form a plurality of multiplexers. Each set of corresponding tri-state repeaters in the plurality of multiplexers share a front end module such that delay through the cross point switch due to input capacitance is reduced as compared to conventional cross point switches.
摘要翻译：根据本发明的一个实施例的交叉点开关包括耦合以形成多个多路复用器的多个三态中继器。多个多路复用器中的每组相应的三态中继器共享前端模块，使得与传统的交叉点开关相比，由于输入电容而导致的交叉点开关的延迟减小。

8. 发明授权

US07661086B1 Enhanced clock signal flexible distribution system and method 有权
标题翻译：增强时钟信号灵活的分配系统和方法
公开(公告)号：US07661086B1
公开(公告)日：2010-02-09
申请号：US11479616
申请日：2006-06-30
申请人： Scott Pitkethly , Robert P. Masleid
发明人： Scott Pitkethly , Robert P. Masleid
IPC分类号： G06F17/50 , H01L29/93 , H01L21/4763
CPC分类号： G06F1/10
摘要： A diagonal offset clock signal distribution system and method are presented that facilitate maximized placement of a diagonal offset clock signal distribution tree.
摘要翻译：提出了一种对角偏移时钟信号分配系统和方法，其促进对角线偏移时钟信号分布树的最大化放置。

9. 发明授权

US07495466B1 Triple latch flip flop system and method 有权
标题翻译：三重锁存触发器系统和方法
公开(公告)号：US07495466B1
公开(公告)日：2009-02-24
申请号：US11480107
申请日：2006-06-30
申请人： Scott Pitkethly , Robert P. Masleid
发明人： Scott Pitkethly , Robert P. Masleid
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K3/356191 , H03K3/012 , H03K17/162 , H03K17/6872
摘要： A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down node. The primary latch records state of the triple latch flip-flop system. The output for outputting a logic value based upon outputs of the pull up latch, pull down latch and the primary latch.
摘要翻译：公开了三重锁存触发器系统和方法。在一个实施例中，三重锁存触发器系统包括上拉锁存器，下拉锁存器，主锁存器和输出端。上拉闩锁驱动一个上拉节点。下拉锁存器驱动下拉节点。主锁存器记录三重锁存触发器系统的状态。用于根据上拉锁存器，下拉锁存器和主锁存器的输出输出逻辑值的输出。

10. 发明授权

US08686778B2 Integrated pulse-control and enable latch circuit 有权
标题翻译：集成脉冲控制和使能锁存电路
公开(公告)号：US08686778B2
公开(公告)日：2014-04-01
申请号：US12546529
申请日：2009-08-24
申请人： Jason M. Hart , Robert P. Masleid
发明人： Jason M. Hart , Robert P. Masleid
IPC分类号： G01R29/02 , H03K9/08 , H03K5/01 , H03K3/017 , H03K5/04 , H03K7/08 , H03K3/00 , H03K3/289
CPC分类号： H03K3/356113 , G06F1/06 , G06F1/10
摘要： The described embodiments provide a configurable clock circuit. The clock circuit includes a control and enable circuit and a clock distribution circuit. During operation, when a signal on an enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a clock mode, the control and enable circuit generates an enable signal on a control output to enable a signal on a clock input to propagate through the clock distribution circuit to the clock output. Alternatively, when a signal on the enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a pulse mode, the control and enable circuit generates a pulsed control signal on the control output to control a length of a pulse generated from the clock input on a clock output by the clock distribution circuit.
摘要翻译：所描述的实施例提供了可配置的时钟电路。时钟电路包括控制和使能电路和时钟分配电路。在操作期间，当控制和使能电路的使能输入上的信号被确认并且控制和使能电路被配置为时钟模式时，控制和使能电路在控制输出上产生使能信号，以使得能够在时钟输入通过时钟分配电路传播到时钟输出。或者，当控制和使能电路的使能输入上的信号被确认并且控制和使能电路被配置为脉冲模式时，控制和使能电路在控制输出上产生脉冲控制信号以控制一个由时钟分配电路输出的时钟上的时钟输入产生的脉冲。

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