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1. 发明申请

US20110072326A1 SRAM MACRO TEST FLOP 有权
标题翻译： SRAM宏测试平台
公开(公告)号：US20110072326A1
公开(公告)日：2011-03-24
申请号：US12565689
申请日：2009-09-23
申请人： Ali Vahidsafa , Robert P. Masleid , Jason M. Hart , Zhirong Feng
发明人： Ali Vahidsafa , Robert P. Masleid , Jason M. Hart , Zhirong Feng
IPC分类号： G06F11/00 , G06F12/00
CPC分类号： G01R31/318541 , G11C11/41 , G11C29/003 , G11C29/22 , G11C29/32 , G11C29/48
摘要： A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master feed-back circuit including a master storage node and a master feed-forward circuit. The slave latch circuit includes a slave feed-back circuit including a slave storage node and a slave feed-forward circuit driven from the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit comprising a scan storage node and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from master latch circuit and a slave driver driven from slave latch circuit.
摘要翻译： SRAM（静态随机存取存储器）宏测试电路包括触发电路，扫描控制电路和输出缓冲电路。触发器电路包括主锁存电路和从锁存电路。主锁存电路包括主反馈电路，主电路包括主存储节点和主前馈电路。从锁存电路包括从主存储节点和从主锁存器驱动的从前馈电路的从属反馈电路。扫描控制电路包括扫描从机前馈电路，扫描锁存电路和由扫描反馈电路驱动的扫描驱动电路。扫描锁存电路包括扫描反馈电路，其包括从从锁存器驱动的扫描存储节点和扫描前馈电路。输出缓冲电路包括从主锁存电路驱动的主驱动器和从从锁存电路驱动的从驱动器。

2. 发明授权

US08181073B2 SRAM macro test flop 有权
标题翻译： SRAM宏测试笔
公开(公告)号：US08181073B2
公开(公告)日：2012-05-15
申请号：US12565689
申请日：2009-09-23
申请人： Ali Vahidsafa , Robert P. Masleid , Jason M. Hart , Zhirong Feng
发明人： Ali Vahidsafa , Robert P. Masleid , Jason M. Hart , Zhirong Feng
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G11C11/41 , G11C29/003 , G11C29/22 , G11C29/32 , G11C29/48
摘要： A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master feed-back circuit including a master storage node and a master feed-forward circuit. The slave latch circuit includes a slave feed-back circuit including a slave storage node and a slave feed-forward circuit driven from the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit comprising a scan storage node and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from master latch circuit and a slave driver driven from slave latch circuit.
摘要翻译： SRAM（静态随机存取存储器）宏测试电路包括触发电路，扫描控制电路和输出缓冲电路。触发器电路包括主锁存电路和从锁存电路。主锁存电路包括主反馈电路，主电路包括主存储节点和主前馈电路。从锁存电路包括从主存储节点和从主锁存器驱动的从前馈电路的从属反馈电路。扫描控制电路包括扫描从机前馈电路，扫描锁存电路和由扫描反馈电路驱动的扫描驱动电路。扫描锁存电路包括扫描反馈电路，其包括从从锁存器驱动的扫描存储节点和扫描前馈电路。输出缓冲电路包括从主锁存电路驱动的主驱动器和从从锁存电路驱动的从驱动器。

3. 发明授权

US08943375B2 Combo static flop with full test 有权
标题翻译：组合静态触发器充分测试
公开(公告)号：US08943375B2
公开(公告)日：2015-01-27
申请号：US13569833
申请日：2012-08-08
申请人： Robert P. Masleid , Ali Vahidsafa
发明人： Robert P. Masleid , Ali Vahidsafa
IPC分类号： G11C29/32 , G11C29/54
CPC分类号： G11C29/32
摘要： A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master storage node and a multiplexer. The slave latch circuit includes a slave storage node driven by the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit, a scan storage node, and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from the master latch circuit and a slave driver driven from the slave latch circuit.
摘要翻译： SRAM（静态随机存取存储器）宏测试电路包括触发电路，扫描控制电路和输出缓冲电路。触发器电路包括主锁存电路和从锁存电路。主锁存电路包括主存储节点和多路复用器。从锁存电路包括由主锁存器驱动的从存储节点。扫描控制电路包括扫描从机前馈电路，扫描锁存电路和由扫描反馈电路驱动的扫描驱动电路。扫描锁存电路包括扫描反馈电路，扫描存储节点和从从锁存器驱动的扫描前馈电路。输出缓冲电路包括从主锁存电路驱动的主驱动器和从从锁存电路驱动的从驱动器。

4. 发明申请

US20140047284A1 COMBO STATIC FLOP WITH FULL TEST 有权
标题翻译：全面测试的COMBO STATIC FLOP
公开(公告)号：US20140047284A1
公开(公告)日：2014-02-13
申请号：US13569833
申请日：2012-08-08
申请人： Robert P. Masleid , Ali Vahidsafa
发明人： Robert P. Masleid , Ali Vahidsafa
IPC分类号： G11C29/08
CPC分类号： G11C29/32
摘要： A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master storage node and a multiplexer. The slave latch circuit includes a slave storage node driven by the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit, a scan storage node, and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from the master latch circuit and a slave driver driven from the slave latch circuit.
摘要翻译： SRAM（静态随机存取存储器）宏测试电路包括触发电路，扫描控制电路和输出缓冲电路。触发器电路包括主锁存电路和从锁存电路。主锁存电路包括主存储节点和多路复用器。从锁存电路包括由主锁存器驱动的从存储节点。扫描控制电路包括扫描从机前馈电路，扫描锁存电路和由扫描反馈电路驱动的扫描驱动电路。扫描锁存电路包括扫描反馈电路，扫描存储节点和从从锁存器驱动的扫描前馈电路。输出缓冲电路包括从主锁存电路驱动的主驱动器和从从锁存电路驱动的从驱动器。

5. 发明授权

US08686778B2 Integrated pulse-control and enable latch circuit 有权
标题翻译：集成脉冲控制和使能锁存电路
公开(公告)号：US08686778B2
公开(公告)日：2014-04-01
申请号：US12546529
申请日：2009-08-24
申请人： Jason M. Hart , Robert P. Masleid
发明人： Jason M. Hart , Robert P. Masleid
IPC分类号： G01R29/02 , H03K9/08 , H03K5/01 , H03K3/017 , H03K5/04 , H03K7/08 , H03K3/00 , H03K3/289
CPC分类号： H03K3/356113 , G06F1/06 , G06F1/10
摘要： The described embodiments provide a configurable clock circuit. The clock circuit includes a control and enable circuit and a clock distribution circuit. During operation, when a signal on an enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a clock mode, the control and enable circuit generates an enable signal on a control output to enable a signal on a clock input to propagate through the clock distribution circuit to the clock output. Alternatively, when a signal on the enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a pulse mode, the control and enable circuit generates a pulsed control signal on the control output to control a length of a pulse generated from the clock input on a clock output by the clock distribution circuit.
摘要翻译：所描述的实施例提供了可配置的时钟电路。时钟电路包括控制和使能电路和时钟分配电路。在操作期间，当控制和使能电路的使能输入上的信号被确认并且控制和使能电路被配置为时钟模式时，控制和使能电路在控制输出上产生使能信号，以使得能够在时钟输入通过时钟分配电路传播到时钟输出。或者，当控制和使能电路的使能输入上的信号被确认并且控制和使能电路被配置为脉冲模式时，控制和使能电路在控制输出上产生脉冲控制信号以控制一个由时钟分配电路输出的时钟上的时钟输入产生的脉冲。

6. 发明申请

US20110043260A1 INTEGRATED PULSE-CONTROL AND ENABLE LATCH CIRCUIT 有权
标题翻译：集成脉冲控制和使能锁存电路
公开(公告)号：US20110043260A1
公开(公告)日：2011-02-24
申请号：US12546529
申请日：2009-08-24
申请人： Jason M. Hart , Robert P. Masleid
发明人： Jason M. Hart , Robert P. Masleid
IPC分类号： H03L7/06
CPC分类号： H03K3/356113 , G06F1/06 , G06F1/10
摘要： The described embodiments provide a configurable clock circuit. The clock circuit includes a control and enable circuit and a clock distribution circuit. During operation, when a signal on an enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a clock mode, the control and enable circuit generates an enable signal on a control output to enable a signal on a clock input to propagate through the clock distribution circuit to the clock output. Alternatively, when a signal on the enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a pulse mode, the control and enable circuit generates a pulsed control signal on the control output to control a length of a pulse generated from the clock input on a clock output by the clock distribution circuit.
摘要翻译：所描述的实施例提供了可配置的时钟电路。时钟电路包括控制和使能电路和时钟分配电路。在操作期间，当控制和使能电路的使能输入上的信号被确认并且控制和使能电路被配置为时钟模式时，控制和使能电路在控制输出上产生使能信号，以使得能够在时钟输入通过时钟分配电路传播到时钟输出。或者，当控制和使能电路的使能输入上的信号被确认并且控制和使能电路被配置为脉冲模式时，控制和使能电路在控制输出上产生脉冲控制信号以控制一个由时钟分配电路输出的时钟上的时钟输入产生的脉冲。

7. 发明申请

US20100301915A1 LATCH WITH SINGLE CLOCKED DEVICE 审中-公开
标题翻译：带单时钟装置的锁扣
公开(公告)号：US20100301915A1
公开(公告)日：2010-12-02
申请号：US12476143
申请日：2009-06-01
申请人： Jason M. Hart , Robert P. Masleid
发明人： Jason M. Hart , Robert P. Masleid
IPC分类号： H03K3/00
CPC分类号： H03K3/356121 , H03K3/35625
摘要： A D-latch circuit includes a feed forward circuit, a full keeper circuit, and an output buffer circuit. The feed forward circuit inputs a clock signal and a data signal. The feed forward circuit is connected to an input of the full keeper circuit. The feed forward circuit is connected to an output of the full keeper circuit and an input of the output buffer circuit. The output buffer circuit outputs an output signal. The D-latch consists of a single clocked device that switches with the clock signal.
摘要翻译： D锁存电路包括前馈电路，全保持器电路和输出缓冲电路。前馈电路输入时钟信号和数据信号。前馈电路连接到全保持电路的输入端。前馈电路连接到全保持器电路的输出端和输出缓冲电路的输入端。输出缓冲电路输出输出信号。 D锁存器由与时钟信号切换的单个时钟设备组成。

8. 发明授权

US07791393B1 Precision falling edge generator 有权
标题翻译：精密下降发生器
公开(公告)号：US07791393B1
公开(公告)日：2010-09-07
申请号：US12420540
申请日：2009-04-08
申请人： Robert P. Masleid , Heechoul Park , Jason M. Hart
发明人： Robert P. Masleid , Heechoul Park , Jason M. Hart
IPC分类号： H03K3/00
CPC分类号： H03K5/1506 , G06F1/10 , H03K5/151 , H03K5/1515
摘要： A clock generating circuit includes a source clock, a first clock generated from the source clock through a first header, a second clock generated from the source clock through a second header and an inverter, wherein the second clock is out of phase with respect to the first clock, a first delayed falling edge clock, wherein the first delayed falling edge clock corresponds to the first clock with a first delayed falling edge, and a second delayed falling edge clock, wherein the second delayed falling edge clock corresponds to the second clock with a second delayed falling edge. The first delayed falling edge clock is generated from a first leading edge path and a first falling edge path, both originating from the source clock, that are inputted to a first delay chain.
摘要翻译：时钟产生电路包括源时钟，通过第一标头从源时钟产生的第一时钟，通过第二标头从源时钟产生的第二时钟和反相器，其中第二时钟相对于第一时钟，第一延迟下降沿时钟，其中第一延迟下降沿时钟对应于具有第一延迟下降沿的第一时钟和第二延迟下降沿时钟，其中第二延迟下降沿时钟对应于第二时钟，第二个延迟下降。第一延迟下降沿时钟从被输入到第一延迟链的源极时钟的第一前沿路径和第一下降沿路径生成。

9. 发明授权

US07777523B1 Level shifter flip-flop 有权
标题翻译：电平移位器触发器
公开(公告)号：US07777523B1
公开(公告)日：2010-08-17
申请号：US12359933
申请日：2009-01-26
申请人： Robert P. Masleid , Jason M. Hart
发明人： Robert P. Masleid , Jason M. Hart
IPC分类号： H03K19/094
CPC分类号： H03K3/356139 , H03K3/35625
摘要： A flip-flop or other state circuit that includes level-shifting functionality. In connection with a flip-flop, embodiments include an inverter circuit element that has a data input line as its input and a data complement line as its output. The inverter resides in voltage domain that is lower than the voltage domain associated with remainder of the flip-flop.
摘要翻译：包括电平转换功能的触发器或其他状态电路。结合触发器，实施例包括具有作为其输入的数据输入线和作为其输出的数据互补线的逆变器电路元件。逆变器的电压域低于与触发器的剩余部分相关联的电压域。

10. 发明授权

US08436668B2 Min-time hardended pulse flop 有权
标题翻译：最小时间硬化脉冲触发器
公开(公告)号：US08436668B2
公开(公告)日：2013-05-07
申请号：US12984174
申请日：2011-01-04
申请人： Robert P. Masleid , Jason M. Hart
发明人： Robert P. Masleid , Jason M. Hart
IPC分类号： H03K3/356
CPC分类号： H03K3/0375
摘要： A flop circuit is disclosed. The flop circuit includes an input circuit configured to hold a logic value of an input signal received on its input node. The flop circuit further includes a storage circuit configured to, responsive to a pulse clock transitioning to a first logic level, receive and store the logic value and a complement of the logic value. A transfer circuit is coupled between the input circuit and the storage circuit, wherein the transfer circuit is configured to transfer the logic value from the input circuit to the storage circuit responsive to the pulse clock transitioning to the first logic level. The transfer circuit includes a first float node and a second float node and is configured such that at least one of the float nodes is floating during a portion of the operational cycle of the flop circuit.
摘要翻译：公开了一种触发电路。触发器电路包括被配置为保持在其输入节点上接收的输入信号的逻辑值的输入电路。触发电路还包括存储电路，其被配置为响应于转换到第一逻辑电平的脉冲时钟，接收并存储逻辑值和逻辑值的补码。传输电路耦合在输入电路和存储电路之间，其中传输电路被配置为响应于脉冲时钟转换到第一逻辑电平而将逻辑值从输入电路传送到存储电路。传输电路包括第一浮点节点和第二浮点节点，并且被配置为使得在触发器电路的操作周期的一部分期间浮动节点中的至少一个浮动。

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