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81. 发明授权

US07883959B2 Semiconductor processing methods 有权
标题翻译：半导体加工方法
公开(公告)号：US07883959B2
公开(公告)日：2011-02-08
申请号：US12855585
申请日：2010-08-12
申请人： Mark Fischer , Terrence B. McDaniel
发明人： Mark Fischer , Terrence B. McDaniel
IPC分类号： H01L21/8234 , H01L21/8244
CPC分类号： H01L23/5225 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a semiconductor substrate. The electrically conductive material can be incorporated into an electrically-grounded shield, and/or can be configured to create a magnetic field bias. Also, the conductive material can have electrically isolated segments that are utilized as electrical jumpers for connecting circuit elements. The invention also includes semiconductor constructions comprising the electrically conductive material between line constructions associated with one or both of the pitch region and the peripheral region.
摘要翻译：本发明包括在与半导体衬底的外围区域或间距区域相关联的线路构造之间形成导电材料的方法。导电材料可以结合到电接地屏蔽中，和/或可以被配置成产生磁场偏置。此外，导电材料可以具有用作连接电路元件的电跳线的电隔离段。本发明还包括在与线圈结构相关联的线路结构之间包括导电材料的半导体结构，其与音调区域和外围区域中的一个或两个相关联。

82. 发明申请

US20100112489A1 EFFICIENT PITCH MULTIPLICATION PROCESS 有权
标题翻译：有效的PITCH MULTIPLICATION PROCESS
公开(公告)号：US20100112489A1
公开(公告)日：2010-05-06
申请号：US12687005
申请日：2010-01-13
申请人： Mark Fischer , Stephen Russell , H. Montgomery Manning
发明人： Mark Fischer , Stephen Russell , H. Montgomery Manning
IPC分类号： G03F7/20 , H05K3/00
CPC分类号： H01L29/06 , H01L21/0338 , H01L21/3088
摘要： Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.
摘要翻译：通过通过掩模处理衬底来形成集成电路的间距倍增和非间距倍数特征，例如集成电路的阵列，接口和外围区域中的特征。通过图案化光刻胶层来形成掩模，该光致抗蚀剂层同时限定对应于集成电路的阵列，界面和外围区域中的特征的掩模元件。将图案转移到无定形碳层。侧壁间隔物形成在图案化无定形碳层的侧壁上。沉积一层保护材料，然后将其图案化以暴露阵列区域中的掩模元件和界面或外围区域的选定部分。除去阵列区域或其它暴露部分中的无定形碳，从而在阵列区域中留下包括独立的，间距倍增的间隔物的图案。去除保护材料，在阵列区域中留下间距倍数间隔物的图案，并在界面和外围区域留下非间距倍增的掩模元件。将图案转移到硬掩模层，通过该硬掩模层蚀刻下面的基底。

83. 发明授权

US07557001B2 Semiconductor processing methods 有权
标题翻译：半导体加工方法
公开(公告)号：US07557001B2
公开(公告)日：2009-07-07
申请号：US11175864
申请日：2005-07-05
申请人： Mark Fischer , Terrence B. McDaniel
发明人： Mark Fischer , Terrence B. McDaniel
IPC分类号： H01L21/8234
CPC分类号： H01L23/5225 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a semiconductor substrate. The electrically conductive material can be incorporated into an electrically-grounded shield, and/or can be configured to create a magnetic field bias. Also, the conductive material can have electrically isolated segments that are utilized as electrical jumpers for connecting circuit elements. The invention also includes semiconductor constructions comprising the electrically conductive material between line constructions associated with one or both of the pitch region and the peripheral region.
摘要翻译：本发明包括在与半导体衬底的外围区域或间距区域相关联的线路构造之间形成导电材料的方法。导电材料可以结合到电接地屏蔽中，和/或可以被配置成产生磁场偏置。此外，导电材料可以具有用作连接电路元件的电跳线的电隔离段。本发明还包括在与线圈结构相关联的线路结构之间包括导电材料的半导体结构，其与音调区域和外围区域中的一个或两个相关联。

84. 发明申请

US20080070165A1 Efficient pitch multiplication process 有权
标题翻译：高效的音调乘法过程
公开(公告)号：US20080070165A1
公开(公告)日：2008-03-20
申请号：US11521851
申请日：2006-09-14
申请人： Mark Fischer , Stephen Russell , H. Montgomery Manning
发明人： Mark Fischer , Stephen Russell , H. Montgomery Manning
IPC分类号： G03F7/26
CPC分类号： H01L29/06 , H01L21/0338 , H01L21/3088
摘要： Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.
摘要翻译：通过通过掩模处理衬底来形成集成电路的间距倍增和非间距倍数特征，例如集成电路的阵列，接口和外围区域中的特征。通过图案化光刻胶层来形成掩模，该光致抗蚀剂层同时限定对应于集成电路的阵列，界面和外围区域中的特征的掩模元件。将图案转移到无定形碳层。侧壁间隔物形成在图案化无定形碳层的侧壁上。沉积一层保护材料，然后将其图案化以暴露阵列区域中的掩模元件和界面或外围区域的选定部分。除去阵列区域或其它暴露部分中的无定形碳，从而在阵列区域中留下包括独立的，间距倍增的间隔物的图案。去除保护材料，在阵列区域中留下间距倍数间隔物的图案，并在界面和外围区域留下非间距倍增的掩模元件。将图案转移到硬掩模层，通过该硬掩模层蚀刻下面的基底。

85. 发明申请

US20070010084A1 Semiconductor processing methods, and semiconductor constructions 有权
标题翻译：半导体加工方法和半导体结构
公开(公告)号：US20070010084A1
公开(公告)日：2007-01-11
申请号：US11175864
申请日：2005-07-05
申请人： Mark Fischer , Terrence McDaniel
发明人： Mark Fischer , Terrence McDaniel
IPC分类号： H01L21/4763
CPC分类号： H01L23/5225 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a semiconductor substrate. The electrically conductive material can be incorporated into an electrically-grounded shield, and/or can be configured to create a magnetic field bias. Also, the conductive material can have electrically isolated segments that are utilized as electrical jumpers for connecting circuit elements. The invention also includes semiconductor constructions comprising the electrically conductive material between line constructions associated with one or both of the pitch region and the peripheral region.
摘要翻译：本发明包括在与半导体衬底的外围区域或间距区域相关联的线路构造之间形成导电材料的方法。导电材料可以结合到电接地屏蔽中，和/或可以被配置成产生磁场偏置。此外，导电材料可以具有电隔离段，其被用作用于连接电路元件的电跳线。本发明还包括在与线圈结构相关联的线路结构之间包括导电材料的半导体结构，其与音调区域和外围区域中的一个或两个相关联。

86. 发明申请

US20060263987A1 Methods of forming fusible devices 审中-公开
标题翻译：形成易熔装置的方法
公开(公告)号：US20060263987A1
公开(公告)日：2006-11-23
申请号：US11496251
申请日：2006-07-31
申请人： Mark Fischer , Zhiping Yin , Thomas Glass , Kunal Parekh , Gurtej Sandhu
发明人： Mark Fischer , Zhiping Yin , Thomas Glass , Kunal Parekh , Gurtej Sandhu
IPC分类号： H01L21/336
CPC分类号： H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a laser fuse. The laser fuse comprises an element comprising a heat conductive material. The fuse also includes an absorption element comprising a material with an adjustable capacity for heat or light absorption that overlays the heat conductive element. The fuse also includes an outer insulating element that overlays and encloses the heat conductive element and the absorption element.
摘要翻译：本发明涉及一种激光熔丝。激光熔丝包括包含导热材料的元件。保险丝还包括吸收元件，该吸收元件包括具有与热传导元件重叠的热或光吸收的可调容量的材料。保险丝还包括覆盖并包围导热元件和吸收元件的外绝缘元件。

87. 发明申请

US20060234469A1 A method of forming semiconductor structures 审中-公开
标题翻译：一种形成半导体结构的方法
公开(公告)号：US20060234469A1
公开(公告)日：2006-10-19
申请号：US11409134
申请日：2006-04-21
申请人： David Dickerson , Richard Lane , Charles Dennison , Kunal Parekh , Mark Fischer , John Zahurak
发明人： David Dickerson , Richard Lane , Charles Dennison , Kunal Parekh , Mark Fischer , John Zahurak
IPC分类号： H01L21/76
CPC分类号： H01L21/76232 , H01L21/0332 , H01L21/76235
摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.
摘要翻译：一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氧化物层; b）在所述氧化物层上形成氮化物层，所述氮化物层和氧化物层具有延伸穿过其中的开口图案以暴露所述下面的衬底的部分; c）蚀刻下面的衬底的暴露部分以形成延伸到衬底中的开口; d）在蚀刻下面的衬底的暴露部分之后，去除氮化物层的部分，同时留下一些保留在衬底上的氮化物层; 以及e）在去除所述氮化物层的部分之后，在所述衬底的所述开口内形成氧化物，所述开口内的氧化物形成至少部分隔离区域。另一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氮化硅层; b）在氮化硅层上形成掩模层; c）形成延伸穿过掩模层的开口图案到氮化硅层; d）将开口穿过氮化硅层延伸到下面的衬底，氮化硅层具有靠近开口的边缘区域，并且在边缘区域之间具有中心区域; e）将开口延伸到下面的基底中; f）在将开口延伸到下面的基底之后，减小边缘区域处的氮化硅层的厚度，以使边缘区域相对于中心区域变薄; 和g）在开口内形成氧化物。

88. 发明申请

US20050211671A1 Oxygen plasma treatment for a nitride surface to reduce photo footing 审中-公开
标题翻译：用于氮化物表面的氧等离子体处理以减少照片基础
公开(公告)号：US20050211671A1
公开(公告)日：2005-09-29
申请号：US11125981
申请日：2005-05-10
申请人： Zhiping Yin , Mark Fischer
发明人： Zhiping Yin , Mark Fischer
IPC分类号： H01L21/027 , H01L21/318 , H01L21/302 , B44C1/22
CPC分类号： H01L21/3105 , H01L21/0274 , H01L21/3185
摘要： The present invention includes a method for preventing distortion in semi-conductor fabrication. The method comprises providing a substrate comprising a film comprising silicon nitride. The substrate is treated in a vacuum of about 3.0-6.5 Torr in an atmosphere comprising oxygen plasma wherein the oxygen plasma flow rate is at least about 300 sccm oxygen. A resist is applied to the treated substrate and the resist is patterned over the treated substrate.
摘要翻译：本发明包括一种用于防止半导体制造中的变形的方法。该方法包括提供包含含氮化硅的膜的衬底。在包含氧等离子体的气氛中，在约3.0-6.5乇的真空中处理衬底，其中氧等离子体流速为至少约300sccm的氧气。将抗蚀剂施加到经处理的基底上，并且将抗蚀剂图案化在经处理的基底上。

89. 发明授权

US06699743B2 Masked nitrogen enhanced gate oxide 失效
标题翻译：用于掩蔽氮增强栅极氧化物的方法
公开(公告)号：US06699743B2
公开(公告)日：2004-03-02
申请号：US10198215
申请日：2002-07-17
申请人： John T. Moore , Mark Fischer
发明人： John T. Moore , Mark Fischer
IPC分类号： H01L218238
CPC分类号： H01L21/823857 , H01L21/28202 , H01L21/3115 , H01L21/3144 , H01L21/823462 , H01L29/518 , H01L29/78
摘要： The present invention provides a method for fabricating improved integrated circuit devices. The method of the present invention enables selective hardening of gate oxide layers and includes providing a semiconductor substrate having a gate oxide layer formed thereover. A resist is then formed over the gate oxide layer and patterned to expose one or more areas of the gate oxide layer which are to be hardened. The exposed portions of the gate oxide layer are then hardened using a true remote plasma nitridation (RPN) scheme or a high-density plasma (HDP) RPN scheme. Because the RPN scheme used in the method of the present invention runs at low temperature, the patterned resist remains stable through the RPN process, and those areas of gate oxide layer which are exposed by the patterned resist are selectively hardened by the RPN treatment, while those areas covered by the patterned resist remain unaffected. The method of the present invention is extremely adaptable and may further include additional thermal oxidation steps used to thicken non-hardened portions of the gate oxide layer, as well as additional masking, and hardening steps, which may provide multiple hardened or non-hardened portions of varying thicknesses within a single gate oxide layer. Thus, the method of the present invention may be used to fabricate an IC device having selectively hardened N-channel and P-channel devices having gate oxides of varying thickness.
摘要翻译：本发明提供一种制造改进的集成电路器件的方法。本发明的方法能够选择性地硬化栅极氧化物层，并且包括提供其上形成有栅氧化层的半导体衬底。然后在栅极氧化物层上形成抗蚀剂，并将其图案化以暴露待硬化的栅极氧化物层的一个或多个区域。然后使用真正的远程等离子体氮化（RPN）方案或高密度等离子体（HDP）RPN方案来硬化栅极氧化物层的暴露部分。由于本发明方法中使用的RPN方案在低温下运行，图案化的抗蚀剂通过RPN工艺保持稳定，并且由图案化的抗蚀剂暴露的那些栅极氧化物层的那些区域通过RPN处理选择性硬化，而由图案化的抗蚀剂覆盖的区域保持不受影响。本发明的方法是非常适用的，并且还可以包括用于增厚栅极氧化物层的非硬化部分的额外的热氧化步骤，以及额外的掩蔽和硬化步骤，其可以提供多个硬化或非硬化部分在单个栅极氧化物层内具有变化的厚度。因此，本发明的方法可用于制造具有选择性硬化的具有不同厚度的栅极氧化物的N沟道和P沟道器件的IC器件。

90. 发明授权

US06461985B1 Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers 有权
公开(公告)号：US06461985B1
公开(公告)日：2002-10-08
申请号：US09393542
申请日：1999-09-10
申请人： John T. Moore , Scott J. DeBoer , Mark Fischer
发明人： John T. Moore , Scott J. DeBoer , Mark Fischer
IPC分类号： H01L2131
CPC分类号： H01L21/3185 , H01L21/32 , H01L21/76202
摘要： In one aspect, the invention includes a method of semiconductive wafer processing comprising forming a silicon nitride layer over a surface of a semiconductive wafer, the silicon nitride layer comprising at least two portions, one of said at least two portions generating a compressive force against the other of the at least two portions, and the other of the at least two portions generating a tensile force against the one of the at least two portions. In another aspect, the invention includes a method of reducing stress on semiconductive wafer, the semiconductive wafer having a pair of opposing surfaces and having more silicon nitride over one of the opposing surfaces than over the other of the opposing surfaces, the method comprising providing the silicon nitride over the one of the opposing surfaces to comprise a first portion, a second portion and a third portion, the first, second and third portions being elevationally displaced relative to one another, the second portion being between the first and third portions, the second portion having a greater stoichiometric amount of silicon than the first and third portions, the semiconductive wafer being subjected to less stress than if the silicon nitride over the one of the opposing surfaces had a constant stoichiometric amount of silicon throughout its thickness. In yet other aspects, the invention includes semiconductive wafer assemblies.

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