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81. 发明授权

US06624513B1 Semiconductor device with multilayer conductive structure formed on a semiconductor substrate 失效
标题翻译：具有形成在半导体衬底上的多层导电结构的半导体器件
公开(公告)号：US06624513B1
公开(公告)日：2003-09-23
申请号：US09787528
申请日：2002-06-26
申请人： Tomio Iwasaki , Hideo Miura , Isamu Asano
发明人： Tomio Iwasaki , Hideo Miura , Isamu Asano
IPC分类号： H01L23532
CPC分类号： H01L21/76843 , H01L21/32051 , H01L21/76844 , H01L21/76846 , H01L21/7685 , H01L21/76852 , H01L21/76877 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A highly reliable semiconductor device having a multilayer structure including an insulating film, an adjacent conductive film, and a main conductive film in which adhesive fractures, voids and disconnections are unlikely to occur. Regarding main constituent elements of the adjacent conductive film and the main conductive film, lattice mismatching is made small, the melting point the adjacent conductive film is set to be not less than 1.4 times that of the main constituent element of the main conductive film, the adjacent conductive film contains at least one different kind of element, the difference between the atomic radius of an added element and that the atomic radius the adjacent conductive film is set to be not more than 10%, and/or bond energy between the added element and silicon (Si) is not less than 1.9 times that of the main constituent element of the adjacent conductive film and silicon (Si).
摘要翻译：具有包括绝缘膜，相邻导电膜和不可能发生粘合剂断裂，空隙和断开的主导电膜的多层结构的高度可靠的半导体器件。关于相邻导电膜和主导电膜的主要构成要素，晶格失配变小，相邻的导电膜的熔点设定为不小于主导电膜的主要构成元素的1.4倍，相邻导电膜含有至少一种不同种类的元素，添加元素的原子半径与相邻导电膜的原子半径之间的差设定为不大于10％，和/或添加元素之间的键能硅（Si）不小于相邻导电膜和硅（Si）的主要构成元素的1.9倍。

82. 发明授权

US06605530B2 Method for fabricating semiconductor integrated circuit 有权
公开(公告)号：US06605530B2
公开(公告)日：2003-08-12
申请号：US10287616
申请日：2002-11-05
申请人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
发明人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
IPC分类号： H01L214763
CPC分类号： H01L27/10852 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

83. 发明授权

US06528888B2 Integrated circuit and method 有权
标题翻译：集成电路及方法
公开(公告)号：US06528888B2
公开(公告)日：2003-03-04
申请号：US09776212
申请日：2001-02-02
申请人： Chih-Chen Cho , Jeffrey A. McKee , William R. McKee , Isamu Asano , Robert Y. Tsu
发明人： Chih-Chen Cho , Jeffrey A. McKee , William R. McKee , Isamu Asano , Robert Y. Tsu
IPC分类号： H01L2348
CPC分类号： H01L27/10894 , H01L21/32051 , H01L21/32053 , H01L27/10811 , H01L27/10885
摘要： An integrated circuit. The circuit includes a memory cell array including wordlines 201 formed on a substrate and bitlines 200 and capacitors 203 formed over the wordlines. The bitlines have a first thickness and pitch. The circuit also includes circuits peripheral to the array including transistors formed in the substrate and conductors 202 over the transistors. The conductors have a second thickness and pitch. The circuit is further characterized in that the bitlines and conductors are formed in a common conductive layer. In further embodiments, the first thickness and pitch are smaller than the second thickness and pitch.
摘要翻译：集成电路。电路包括存储单元阵列，其包括形成在基板上的字线201和位线200上形成的位线200和电容器203。位线具有第一厚度和间距。电路还包括阵列外围的电路，包括形成在衬底中的晶体管和晶体管上的导体202。导体具有第二厚度和间距。电路的特征还在于，位线和导体形成在公共导电层中。在另外的实施例中，第一厚度和间距小于第二厚度和间距。

84. 发明授权

US5811316A Method of forming teos oxide and silicon nitride passivation layer on aluminum wiring 失效
标题翻译：在铝线上形成氧化硅和氮化硅钝化层的方法
公开(公告)号：US5811316A
公开(公告)日：1998-09-22
申请号：US460931
申请日：1995-06-05
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78 , H01L21/28
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L27/0922 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L27/0928 , H01L27/10808 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

85. 发明授权

US5504029A Method of producing semiconductor integrated circuit device having memory cell and peripheral circuit MISFETs 失效
标题翻译：具有存储单元和外围电路MISFET的半导体集成电路器件的制造方法
公开(公告)号：US5504029A
公开(公告)日：1996-04-02
申请号：US254562
申请日：1994-06-06
申请人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
发明人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/105 , H01L27/10808
摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. The impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. The Y-select signal line overlaps the lower electrode layer of the capacitor element. A potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. The dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. The capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure. An aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; and a refractory metal, or a refractory metal silicide QSi.sub.x, where Q is a refractory metal and x is between 0 and 2, is used as a protective layer, for an aluminum wiring containing an added element (e.g., Cu) to prevent migration.
摘要翻译：公开了一种具有开关MISFET的半导体集成电路器件和形成在半导体衬底上的电容器元件。电容器元件连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。 Y选择信号线与电容器元件的下电极层重叠。至少在与电容器元件连接的开关MISFET的半导体区域下方设置的势垒层通过用于沟道阻挡区域的杂质的扩散而形成。电容器元件的电介质膜与其上的电容器电极层共同扩展。电容器电介质膜是其上具有氧化硅层的氮化硅膜，氧化硅层通过在高压下氧化氮化硅的表面层而形成。通过溅射在相同的真空溅射室中形成铝布线层和保护（和/或阻挡层），而不破坏形成层之间的真空; 和难熔金属或难熔金属硅化物QSix，其中Q是难熔金属，x在0和2之间，用作含有添加元素（例如Cu）以防止迁移的铝布线的保护层。

86. 发明授权

US5331191A Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same 失效
标题翻译：半导体集成电路装置及其制造方法及其制造装置
公开(公告)号：US5331191A
公开(公告)日：1994-07-19
申请号：US954142
申请日：1992-09-30
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/10
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L27/0922 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L27/0928 , H01L27/10808 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区和非活性区域的全部表面部分中的方式，在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

87. 发明授权

US5128744A Semiconductor integrated circuit and method of manufacturing same 失效
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US5128744A
公开(公告)日：1992-07-07
申请号：US406062
申请日：1989-09-12
申请人： Isamu Asano , Hideo Aoki
发明人： Isamu Asano , Hideo Aoki
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522
CPC分类号： H01L23/5226 , H01L21/76801 , H01L21/76834 , H01L2924/0002
摘要： In a semiconductor integrated circuit device having a fine multilayer interconnection structure, a wiring material such as tungsten is formed on a predetermined part of the interior of a wiring layer-forming groove formed in a flat inter-layer insulating film by selective deposition. The flat inter-layer insulating film has a laminate structure of two or more insulating films different in etching speed, and a (first) insulating film, underlying a (second) insulating film in which the wiring layer-forming groove of the inter-layer insulating film is formed, serves as an etching stopper to make the depth of the wiring layer-forming groove constant when forming the groove from etching. Consequently, the depth of the wiring layer-forming groove can be defined accurately by the thickness of a (second) insulating film formed by deposition, and the film thickness between wiring layers can be accurately defined by the thickness of an insulating film formed by deposition.
摘要翻译：在具有精细多层互连结构的半导体集成电路器件中，通过选择性沉积在形成在平坦的层间绝缘膜中的布线层形成沟槽的内部的预定部分上形成诸如钨的布线材料。平坦的层间绝缘膜具有两个以上的蚀刻速度不同的绝缘膜的叠层结构，以及在第（第二）绝缘膜的下面的（第一）绝缘膜，其中层间的布线层形成槽形成绝缘膜，作为蚀刻停止层，以便在从蚀刻形成沟槽时使布线层形成槽的深度保持恒定。因此，可以通过沉积形成的（第二）绝缘膜的厚度来精确地限定布线层形成槽的深度，并且可以通过沉积形成的绝缘膜的厚度来精确地限定布线层之间的膜厚度。

88. 发明授权

US08513638B2 Semiconductor device including a phase-change memory element 失效
标题翻译：包括相变存储元件的半导体器件
公开(公告)号：US08513638B2
公开(公告)日：2013-08-20
申请号：US13137687
申请日：2011-09-02
申请人： Tomoyasu Kakegawa , Isamu Asano , Tsuyoshi Kawagoe , Hiromi Sasaoka , Naoya Higano , Yuta Watanabe
发明人： Tomoyasu Kakegawa , Isamu Asano , Tsuyoshi Kawagoe , Hiromi Sasaoka , Naoya Higano , Yuta Watanabe
IPC分类号： H01L29/02
CPC分类号： H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1675
摘要： A semiconductor device may include, but is not limited to: a first insulating film; a second insulating film over the first insulating film; a first memory structure between the first and second insulating films; and a third insulating film between the first and second insulating films. The first memory structure may include, but is not limited to: a heater electrode; and a phase-change memory element between the heater electrode and the second insulating film. The phase-change memory element contacts the heater electrode. The third insulating film covers at least a side surface of the phase-change memory element. Empty space is positioned adjacent to at least one of the heater electrode and the third insulating film.
摘要翻译：半导体器件可以包括但不限于：第一绝缘膜; 第一绝缘膜上的第二绝缘膜; 第一和第二绝缘膜之间的第一存储器结构; 以及在第一和第二绝缘膜之间的第三绝缘膜。第一存储器结构可以包括但不限于：加热器电极; 以及加热器电极和第二绝缘膜之间的相变存储元件。相变存储元件接触加热器电极。第三绝缘膜覆盖相变存储元件的至少一个侧面。空的空间位于与加热器电极和第三绝缘膜中的至少一个相邻的位置。

89. 发明授权

US07985693B2 Method of producing phase change memory device 有权
标题翻译：相变存储器件的制造方法
公开(公告)号：US07985693B2
公开(公告)日：2011-07-26
申请号：US12289002
申请日：2008-10-17
申请人： Akiyoshi Seko , Natsuki Sato , Isamu Asano
发明人： Akiyoshi Seko , Natsuki Sato , Isamu Asano
IPC分类号： H01L21/302
CPC分类号： H01L45/1233 , G11C13/0004 , H01L27/2472 , H01L45/04 , H01L45/06 , H01L45/1273 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/16
摘要： An area where a lower electrode is in contact with a variable resistance material needs to be reduced to lower the power consumption of a variable resistance memory device. The present invention is to provide a method of producing a variable resistance memory element whereby the lower electrode can be formed smaller. Combining an anisotropic etching process with an isotropic etching process enables the lower electrode to be formed smaller.
摘要翻译：需要减小下电极与可变电阻材料接触的区域，以降低可变电阻存储器件的功耗。本发明提供一种制造可变电阻存储元件的方法，由此可以使下电极形成得更小。将各向异性蚀刻工艺与各向同性蚀刻工艺相结合，能够使下部电极形成得更小。

90. 发明申请

US20100302842A1 SEMICONDUCTOR MEMORY DEVICE, MANUFACTURING METHOD THEREOF, DATA PROCESSING SYSTEM, AND DATA PROCESSING DEVICE 审中-公开
标题翻译：半导体存储器件，其制造方法，数据处理系统和数据处理器件
公开(公告)号：US20100302842A1
公开(公告)日：2010-12-02
申请号：US12792296
申请日：2010-06-02
申请人： Tsuyoshi KAWAGOE , Isamu Asano
发明人： Tsuyoshi KAWAGOE , Isamu Asano
IPC分类号： G11C11/00 , H01L45/00 , H01L21/04
CPC分类号： H01L27/11517 , G11C13/0004 , G11C2213/72 , H01L27/1021 , H01L27/115 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/148
摘要： A semiconductor memory device includes: first and second impurity diffusion layers that form a part of a semiconductor substrate, each of the impurity diffusion layers function as one and the other of an anode and a cathode, respectively of a pn-junction diode; a recording layer connected to the second impurity diffusion layer; and a cylindrical sidewall insulation film provided on the first impurity diffusion layer. At least a part of the second diffusion layer and at least a part of the recording layer are formed in a region surrounded by a sidewall insulation film. According to the present invention, because a pillar-shaped pn-junction diode and the recording layer are formed in a self-aligned manner, the degree of integration of a semiconductor memory device can be increased. Further, because a silicon pillar is a part of the semiconductor substrate, a leakage current attributable to a crystal defect can be reduced.
摘要翻译：半导体存储器件包括：形成半导体衬底的一部分的第一和第二杂质扩散层，每个杂质扩散层分别作为pn结二极管的阳极和阴极的一个和另一个起作用; 连接到第二杂质扩散层的记录层; 以及设置在第一杂质扩散层上的圆筒形侧壁绝缘膜。第二扩散层的至少一部分和记录层的至少一部分形成在由侧壁绝缘膜包围的区域中。根据本发明，由于柱状pn结二极管和记录层以自对准的方式形成，所以可以提高半导体存储器件的集成度。此外，由于硅柱是半导体衬底的一部分，所以可以减少归因于晶体缺陷的漏电流。

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