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    • 82. 发明授权
    • Steering column device
    • 转向柱装置
    • US07350813B2
    • 2008-04-01
    • US10522173
    • 2003-07-25
    • Koji Inoue
    • Koji Inoue
    • B62D1/18
    • B62D1/184
    • A steering column apparatus comprising: a steering column provided with a body-side bracket mounted to a body strength member to have a pair of side plate portions opposed each other to be extended in a vertical direction, and a substantially cylindrical distance unit for supporting a steering shaft to be rotatable therein and having a pair of pressed and expanding portions formed to be expanded by plastic working to be pressed and supported by the side plate portions of the body-side bracket; and an adjusting mechanism capable of adjusting a position of the steering column with respect to the side plate portions of the body-side bracket within a predetermined range, wherein the steering column is formed with a reinforcement portion for enhancing the clamping rigidity of the distance unit with respect to the side plate portions.
    • 一种转向柱装置,包括:转向柱,其设置有安装在主体部件上的主体侧支架,以具有彼此相对的一对侧板部分,以在垂直方向上延伸;以及大致圆柱形的距离单元, 转向轴可在其中旋转,并具有一对压缩膨胀部分,形成为通过塑料加工而膨胀以被压制并由主体侧托架的侧板部分支撑; 以及能够将转向柱相对于车体侧支架的侧板部的位置调整在预定范围内的调节机构,其中转向柱形成有用于增强距离单元的夹紧刚度的加强部 相对于侧板部。
    • 84. 发明申请
    • Semiconductor memory device
    • 半导体存储器件
    • US20050169038A1
    • 2005-08-04
    • US11045786
    • 2005-01-28
    • Koji InoueYoshinao MorikawaAtsushi ShimaokaYukio Tamai
    • Koji InoueYoshinao MorikawaAtsushi ShimaokaYukio Tamai
    • G11C11/15G11C7/06G11C7/12G11C7/14G11C8/08G11C11/00
    • G11C7/062G11C7/06G11C7/12G11C7/14G11C8/08
    • A semiconductor memory device comprises a column readout voltage supply circuit which supplies a predetermined first voltage when readout is selected and supplies a predetermined second voltage which is different from the fist voltage when the readout is not selected, to each column selection line, a row readout voltage supply circuit which supplies the second voltage to each row selection line at the time of readout, a sense circuit which detects a current flowing in the selected row selection line separately from a current flowing in the non-selected row selection lines to detect an electric resistance state of the selected memory cell at the time of readout, and a column voltage displacement prevention circuit which prevents displacement of a supplied voltage level for each of the non-selected column selection lines at the time of readout.
    • 半导体存储器件包括列读出电压供应电路,当选择读出时提供预定的第一电压,并且当未选择读出时将提供与第一电压不同的预定的第二电压提供给每列选择线,行读出 电压供给电路,其在读出时向每行行选择线提供第二电压;感测电路,其检测在所选行行选择线中流动的电流与流过未选择行选择线的电流分开,以检测电 在读出时所选择的存储单元的电阻状态和列电压位移防止电路,用于在读出时防止每个未选择的列选择线提供的电压电平的位移。
    • 85. 发明授权
    • Nonvolatile memory device
    • 非易失性存储器件
    • US06888745B2
    • 2005-05-03
    • US10730190
    • 2003-12-04
    • Masayuki EhiroKoji InoueNobuyoshi Awaya
    • Masayuki EhiroKoji InoueNobuyoshi Awaya
    • G11C11/15G11C11/56G11C13/00G11C16/02H01L27/10H01L27/105H01L45/00G11C11/00
    • G11C13/0007G11C11/5685G11C2213/31G11C2213/79
    • An object of the present invention is to provide a mass-storage nonvolatile memory device capable of performing high speed operation. The nonvolatile memory device comprises a memory array comprising a plurality of memory cells arranged in a matrix, each of the memory cells comprising a variable resistor element formed of a manganese-containing oxide having a perovskite structure in which an electric resistance is varied by application of a voltage pulse and a variation amount of the electric resistance is variable depending on the magnitude of the voltage amplitude; and a program pulse generation circuit that, in order to program 3-level or larger multi-level data corresponding to one erase state and two or more program states into the variable resistor element, is capable of performing generation of program pulses having two or more different voltage amplitudes corresponding to the program states, the generation being separately performed corresponding to program data.
    • 本发明的目的是提供一种能够执行高速操作的大容量存储非易失性存储装置。 非易失性存储器件包括存储器阵列,其包括以矩阵形式布置的多个存储器单元,每个存储器单元包括由具有钙电结构的含锰氧化物形成的可变电阻器元件,其中通过施加电阻来改变电阻 电压脉冲和电阻的变化量根据电压振幅的大小而变化; 以及编程脉冲发生电路,为了将对应于一个擦除状态和两个或更多个编程状态的3级或更大的多电平数据编程到可变电阻器元件中,能够执行具有两个或更多个 对应于程序状态的不同的电压幅度,对应于程序数据单独执行生成。
    • 87. 发明授权
    • Cache memory system with variable block-size mechanism
    • 具有可变块大小机制的缓存存储器系统
    • US06349364B1
    • 2002-02-19
    • US09270254
    • 1999-03-15
    • Koji KaiKoji InoueKazuaki Murakami
    • Koji KaiKoji InoueKazuaki Murakami
    • G06F1204
    • G06F12/0886
    • The present invention provides for setting the block-size suitably in each address space in order to deal with the difference of the scope within the spatial locality in the address space, and to suppress the generating of the unnecessary replacing. In a cache memory system according to the present invention, a cache memory is provided for temporarily storing the data stored in a main memory, and a processor accesses the cache memory, the cache memory system comprising: a block-size information storing system for storing the size of the data to be replaced between the cache memory and the main memory in every plural storage spaces of predetermined amount within the cache memory; and a system for replacing the data between the storage space in which the cache miss is occurred within the cache memory and the main memory, when the access of the processor to the storage space within the cache memory produces a cache miss, at the block-size corresponding to the storage space producing the cache miss, among the size stored in the block-size information storing system.
    • 本发明提供了在每个地址空间中适当地设置块大小,以便处理地址空间中的空间局部中的范围的差异,并且抑制不必要的替换的产生。 在根据本发明的高速缓冲存储器系统中,提供了一个用于临时存储存储在主存储器中的数据的高速缓冲存储器,并且处理器访问高速缓存存储器,该高速缓冲存储器系统包括:块大小信息存储系统,用于存储 在高速缓冲存储器内的预定量的每个多个存储空间中的高速缓冲存储器和主存储器之间要被替换的数据的大小; 以及用于在处理器到高速缓存存储器内的存储空间的访问产生高速缓存未命中时,替换在高速缓存存储器和主存储器之间发生高速缓存未命中的存储空间之间的数据的系统, 与存储在块大小信息存储系统中的大小相对应的产生高速缓存未命中的存储空间的大小。