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    • 9. 发明授权
    • Playback apparatus and playback method
    • 播放设备和播放方法
    • US5987082A
    • 1999-11-16
    • US889743
    • 1997-07-10
    • Kensuke Fujimoto
    • Kensuke Fujimoto
    • G01R25/00G11B20/10G11B20/14H03H17/00H03L7/085H04L7/00
    • G11B20/1403G11B20/10009
    • To reduce a data-error rate caused by interpolation errors. An adder computes the sum of a sampled value Si+1 of a playback signal and a value 8.times.Si+1 produced by a bit shifter to output the sum 9.times.Si+1 to an adder. The adder adds the sum (9.times.Si+1) supplied thereto by the adder to a sum (9.times.Si) supplied thereto after being delayed by a delay element and outputs the result of the addition (9.times.Si+9.times.Si+1) to an adder. An adder computes the sum of a sampled value Si-1 supplied thereto after being delayed by delay elements and a sampled value Si+2 supplied thereto by an A/D converter and outputs sum (Si-1+Si+2) to the adder. The adder which is used as a subtractor computes the difference between the sum (9.times.Si+9.times.Si+1) supplied thereto by the adder and the sum (Si-1+Si+2) supplied thereto by the adder and outputs the difference (Si-1-9.times.Si-9.times.Si+1+Si+2) to a bit shifter. The bit shifter shifts the difference (Si-1-9.times.Si-9.times.Si+1+Si+2) supplied thereto by the adder by four bits toward the LSB and outputs the right-shifted value (Si-1-9.times.Si-9.times.Si+1+Si+2)/16 to a second interpolation circuit as a first interpolation value Si' along with the sampled values Si and Si+1. As a result, the number of sampled values seemingly appears increased.
    • 减少由插补误差引起的数据错误率。 加法器计算重放信号的采样值Si + 1和由比特移位器产生的值8xSi + 1的和,以将和9xSi + 1输出到加法器。 加法器将由加法器提供的和(9xSi + 1)加到由延迟元件延迟后提供给它的和(9xSi),并将相加结果(9xSi + 9xSi + 1)输出到加法器。 加法器计算由延迟元件延迟后提供给其的采样值Si-1和由A / D转换器提供给其的采样值Si + 2的和,并将加法(Si-1 + Si + 2)加到加法器 。 用作减法器的加法器计算由加法器提供给它的和(9xSi + 9xSi + 1)与由加法器提供给它的和(Si-1 + Si + 2)之间的差值,并输出差值(Si- 1-9xSi-9xSi + 1 + Si + 2)到位移位器。 位移器将由加法器提供给其的差(Si-1-9xSi-9xSi + 1 + Si + 2)向LSB移位四位,并输出右移位值(Si-1-9xSi-9xSi + 1 + Si + 2)/ 16连接到作为第一插值值Si'的第二插值电路以及采样值Si和Si + 1。 因此,采样值的数量看起来似乎增加了。