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1. 发明授权

US06888745B2 Nonvolatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US06888745B2
公开(公告)日：2005-05-03
申请号：US10730190
申请日：2003-12-04
申请人： Masayuki Ehiro , Koji Inoue , Nobuyoshi Awaya
发明人： Masayuki Ehiro , Koji Inoue , Nobuyoshi Awaya
IPC分类号： G11C11/15 , G11C11/56 , G11C13/00 , G11C16/02 , H01L27/10 , H01L27/105 , H01L45/00 , G11C11/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C2213/31 , G11C2213/79
摘要： An object of the present invention is to provide a mass-storage nonvolatile memory device capable of performing high speed operation. The nonvolatile memory device comprises a memory array comprising a plurality of memory cells arranged in a matrix, each of the memory cells comprising a variable resistor element formed of a manganese-containing oxide having a perovskite structure in which an electric resistance is varied by application of a voltage pulse and a variation amount of the electric resistance is variable depending on the magnitude of the voltage amplitude; and a program pulse generation circuit that, in order to program 3-level or larger multi-level data corresponding to one erase state and two or more program states into the variable resistor element, is capable of performing generation of program pulses having two or more different voltage amplitudes corresponding to the program states, the generation being separately performed corresponding to program data.
摘要翻译：本发明的目的是提供一种能够执行高速操作的大容量存储非易失性存储装置。非易失性存储器件包括存储器阵列，其包括以矩阵形式布置的多个存储器单元，每个存储器单元包括由具有钙电结构的含锰氧化物形成的可变电阻器元件，其中通过施加电阻来改变电阻电压脉冲和电阻的变化量根据电压振幅的大小而变化; 以及编程脉冲发生电路，为了将对应于一个擦除状态和两个或更多个编程状态的3级或更大的多电平数据编程到可变电阻器元件中，能够执行具有两个或更多个对应于程序状态的不同的电压幅度，对应于程序数据单独执行生成。

2. 发明授权

US08036017B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08036017B2
公开(公告)日：2011-10-11
申请号：US12563349
申请日：2009-09-21
申请人： Nobuyoshi Awaya , Takashi Nakano
发明人： Nobuyoshi Awaya , Takashi Nakano
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/005 , G11C13/0004 , G11C13/0011 , G11C13/0033 , G11C14/00 , G11C14/0045 , G11C2211/4016 , G11C2213/31 , H01L27/2436 , H01L27/2454 , H01L27/2472 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/146
摘要： An inexpensive nonvolatile memory having high performance which makes random write and readout possible an unlimited number of times is provided. A unit memory cell is formed of a MISFET having a channel body that is electrically isolated from a semiconductor substrate and a resistance change element having a two-terminal structure with one end electrically connected to a drain of the MISFET. The MISFET functions as a volatile memory element, and the resistance change element functions as a nonvolatile memory element, so that information stored in the MISFET is copied to the resistance change element before the power is turned OFF and information stored in the resistance change element is transferred to the MISFET when the power is turned ON, and thus, the MISFET is used as a volatile memory which makes random write and readout possible.
摘要翻译：提供了具有高性能的便宜的非易失性存储器，其使得随机写入和读出可能无限次。单元存储单元由具有与半导体基板电隔离的沟道体的MISFET和具有与MISFET的漏极电连接的一端的两端结构的电阻变化元件形成。 MISFET用作易失性存储元件，并且电阻变化元件用作非易失性存储元件，使得存储在MISFET中的信息在电源断开之前被复制到电阻变化元件，并且存储在电阻变化元件中的信息是当电源接通时转移到MISFET，因此，MISFET被用作使随机写入和读出成为可能的易失性存储器。

3. 发明授权

US07894239B2 Variable resistance element, method for producing the same, and nonvolatile semiconductor storage device 有权
标题翻译：可变电阻元件及其制造方法以及非易失性半导体存储器件
公开(公告)号：US07894239B2
公开(公告)日：2011-02-22
申请号：US12328648
申请日：2008-12-04
申请人： Yukio Tamai , Yasunari Hosoi , Nobuyoshi Awaya , Shigeo Ohnishi , Kazuya Ishihara , Hisashi Shima , Fumiyoshi Takano , Hiroyuki Akinaga
发明人： Yukio Tamai , Yasunari Hosoi , Nobuyoshi Awaya , Shigeo Ohnishi , Kazuya Ishihara , Hisashi Shima , Fumiyoshi Takano , Hiroyuki Akinaga
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C13/0007 , G11C13/0028 , G11C2013/0083 , G11C2213/32 , G11C2213/56 , G11C2213/77 , H01C7/108 , H01L45/04 , H01L45/1233 , H01L45/1246 , H01L45/146 , H01L45/1658 , Y10T29/49082
摘要： The variable resistance element of the present invention is a variable resistance element having an electrode, the other electrode, and a metal oxide material sandwiched between the electrodes and having an electrical resistance, between the electrodes, changing reversibly in response to a voltage applied between the electrodes. The variable resistance element further includes, inside the metal oxide material, a low resistance material having a lower electrical resistance than the metal oxide material and being out of contact with at least either one of the electrodes. This makes it possible to reduce a forming voltage for providing a conductive section inside the metal oxide material, without causing a leakage current to increase.
摘要翻译：本发明的可变电阻元件是具有电极，另一个电极和夹在电极之间并具有电阻的金属氧化物材料的可变电阻元件，在电极之间，响应于施加在电极之间的电压而可逆地改变电极。可变电阻元件还包括在金属氧化物材料内部的具有比金属氧化物材料低的电阻并且与至少任一个电极不接触的低电阻材料。这使得可以降低用于在金属氧化物材料内部提供导电部分的形成电压，而不会导致泄漏电流增加。

4. 发明申请

US20090147558A1 VARIABLE RESISTANCE ELEMENT, METHOD FOR PRODUCING THE SAME, AND NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：可变电阻元件，其制造方法和非易失性半导体存储器件
公开(公告)号：US20090147558A1
公开(公告)日：2009-06-11
申请号：US12328648
申请日：2008-12-04
申请人： Yukio Tamai , Yasunari Hosoi , Nobuyoshi Awaya , Shigeo Ohnishi , Kazuya Ishihara , Hisashi Shima , Fumiyoshi Takano , Hiroyuki Akinaga
发明人： Yukio Tamai , Yasunari Hosoi , Nobuyoshi Awaya , Shigeo Ohnishi , Kazuya Ishihara , Hisashi Shima , Fumiyoshi Takano , Hiroyuki Akinaga
IPC分类号： G11C11/21 , H01C7/10 , H01C17/00
CPC分类号： G11C8/08 , G11C13/0007 , G11C13/0028 , G11C2013/0083 , G11C2213/32 , G11C2213/56 , G11C2213/77 , H01C7/108 , H01L45/04 , H01L45/1233 , H01L45/1246 , H01L45/146 , H01L45/1658 , Y10T29/49082
摘要： The variable resistance element of the present invention is a variable resistance element having an electrode, the other electrode, and a metal oxide material sandwiched between the electrodes and having an electrical resistance, between the electrodes, changing reversibly in response to a voltage applied between the electrodes. The variable resistance element further includes, inside the metal oxide material, a low resistance material having a lower electrical resistance than the metal oxide material and being out of contact with at least either one of the electrodes. This makes it possible to reduce a forming voltage for providing a conductive section inside the metal oxide material, without causing a leakage current to increase.
摘要翻译：本发明的可变电阻元件是具有电极，另一个电极和夹在电极之间并具有电阻的金属氧化物材料的可变电阻元件，在电极之间，响应于施加在电极之间的电压而可逆地改变电极。可变电阻元件还包括在金属氧化物材料内部的具有比金属氧化物材料低的电阻并且与至少任一个电极不接触的低电阻材料。这使得可以降低用于在金属氧化物材料内部提供导电部分的形成电压，而不会导致泄漏电流增加。

5. 发明申请

US20080169569A1 Bonding pad of semiconductor integrated circuit, method for manufacturing the bonding pad, semiconductor integrated circuit, and electronic device 审中-公开
标题翻译：半导体集成电路的接合焊盘，用于制造接合焊盘的方法，半导体集成电路和电子器件
公开(公告)号：US20080169569A1
公开(公告)日：2008-07-17
申请号：US12003718
申请日：2007-12-31
申请人： Kazuya Ishihara , Nobuyoshi Awaya
发明人： Kazuya Ishihara , Nobuyoshi Awaya
IPC分类号： H01L23/488
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05006 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05558 , H01L2224/05567 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/451 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/05042 , H01L2924/14 , H01L2224/48 , H01L2224/05552
摘要： According to the present invention, a bonding pad 10 of a semiconductor integrated circuit is arranged such that the opening pathways P through which metal wiring layers are connected have openings of at least two different widths including: a first width required to fill the opening pathway; and a second width being larger than the first width, and the openings are arranged lengthwise and crosswise.
摘要翻译：根据本发明，半导体集成电路的接合焊盘10被布置成使得金属布线层连接的开口通路P具有至少两个不同宽度的开口，包括：填充开口路径所需的第一宽度; 并且第二宽度大于第一宽度，并且开口纵向和横向设置。

6. 发明授权

US06956280B2 Integrated circuit apparatus and neuro element 有权
标题翻译：集成电路设备和神经元件
公开(公告)号：US06956280B2
公开(公告)日：2005-10-18
申请号：US10397090
申请日：2003-03-25
申请人： Masayuki Tajiri , Nobuyoshi Awaya
发明人： Masayuki Tajiri , Nobuyoshi Awaya
IPC分类号： H01L27/10 , G06N3/063 , G11C11/54 , G11C13/00 , H01L49/00 , H01L29/00
CPC分类号： G11C13/0007 , G06N3/063 , G11C11/54 , G11C2213/31
摘要： Input signals are weighted by weighting means composed of variable resistors, each made of an oxide thin film with a perovskite structure containing manganese, which changes resistance at room temperature according to the cumulative number of times a pulse voltage was applied and holds the resistance in a nonvolatile manner. Then, the weighted signals are inputted to an arithmetic unit. The oxide thin film used as each of the variable resistors changes its resistance, according to the cumulative number of times the input pulse was applied, and further holds the resistance in a nonvolatile manner even after the power supply is cut off. Thus, by changing the weighting factor according to the cumulative number of times the pulse voltage was applied, a neuro element more resembling a neuron of the human being is realized.
摘要翻译：输入信号通过由可变电阻器组成的加权装置加权，每个可变电阻器由具有包含锰的钙钛矿结构的氧化物薄膜制成，其根据施加脉冲电压的累积次数在室温下改变电阻并且将电阻保持在非挥发性。然后，加权信号被输入到运算单元。用作各可变电阻器的氧化物薄膜根据施加输入脉冲的累积次数而改变其电阻，并且即使在电源被切断之后也进一步保持电阻以非易失性方式。因此，通过根据施加脉冲电压的累积次数来改变加权因子，实现了更类似于人的神经元的神经元素。

7. 发明授权

US06711049B1 One transistor cell FeRAM memory array 失效
标题翻译：一个晶体管单元FeRAM存储器阵列
公开(公告)号：US06711049B1
公开(公告)日：2004-03-23
申请号：US10282985
申请日：2002-10-28
申请人： Sheng Teng Hsu , Jong-Jan Lee , Fengyan Zhang , Nobuyoshi Awaya
发明人： Sheng Teng Hsu , Jong-Jan Lee , Fengyan Zhang , Nobuyoshi Awaya
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A one-transistor FeRAM memory cell array includes an array of ferroelectric transistors arranged in rows and columns, each transistor having a source, a drain, a channel, a gate oxide layer over the channel and a ferroelectric stack formed on the gate oxide layer; word lines connecting the gate ferroelectric stack top electrodes of transistors in a row of the array; a connection to the channel of all transistors in the array formed by a substrate well; a set of first bit lines connecting the sources of all transistors in a column of the array; and a set of second bit lines connecting the drains of all transistors in a column of the array; wherein the ferroelectric stack has opposed edges, which, when projected to a level of the source, drain and channel, are coincident with an abutted edge of the source and the channel and the drain and the channel, respectively.
摘要翻译：单晶体管FeRAM存储单元阵列包括以行和列布置的铁电晶体管阵列，每个晶体管具有源极，漏极，沟道，沟道上的栅极氧化物层和形成在栅极氧化物层上的铁电堆叠; 连接阵列中的晶体管的栅极铁电叠层顶部电极的字线; 连接到由衬底阱形成的阵列中的所有晶体管的沟道; 连接阵列的列中的所有晶体管的源的一组第一位线; 以及连接阵列中的所有晶体管的漏极的一组第二位线; 其中所述铁电堆叠具有相对的边缘，当所述铁电堆叠被投影到所述源极的水平面时，所述漏极和沟道分别与所述源极和所述沟道以及所述漏极和所述沟道的邻接边缘重合。

8. 发明授权

US08482956B2 Semiconductor memory device and method of driving the same 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US08482956B2
公开(公告)日：2013-07-09
申请号：US13179839
申请日：2011-07-11
申请人： Shinobu Yamazaki , Yoshiji Ohta , Kazuya Ishihara , Mitsuru Nakura , Suguru Kawabata , Nobuyoshi Awaya
发明人： Shinobu Yamazaki , Yoshiji Ohta , Kazuya Ishihara , Mitsuru Nakura , Suguru Kawabata , Nobuyoshi Awaya
IPC分类号： G11C11/21
CPC分类号： G11C13/0007 , G11C7/1048 , G11C7/12 , G11C13/0004 , G11C13/0026 , G11C13/0038 , G11C13/0069 , G11C2013/0071 , G11C2213/79 , G11C2213/82
摘要： A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line.
摘要翻译：半导体存储器件包括：存储单元阵列，其中多个存储单元以矩阵形式布置，每个存储单元串联连接两端型存储元件和晶体管供选择;第一施加电压电路，电压脉冲到位线，以及第二电压施加电路，其向位线和公共线施加预充电电压。在写入存储单元时，在第二电压施加电路具有先前预充电至相同电压的存储单元的两端，第一电压施加电路经由位线将写入电压脉冲施加到写入目标存储单元的一个端子，并且当施加写入电压脉冲时，第二电压施加电路通过公共线路将预充电电压保持到存储单元的另一个端子。

9. 发明申请

US20100219392A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD FOR SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20100219392A1
公开(公告)日：2010-09-02
申请号：US12713223
申请日：2010-02-26
申请人： Nobuyoshi Awaya , Yoshiji Ohta , Yoshiaki Tabuchi
发明人： Nobuyoshi Awaya , Yoshiji Ohta , Yoshiaki Tabuchi
IPC分类号： H01L45/00 , H01L21/822
CPC分类号： H01L27/249 , G11C13/0007 , G11C2013/0083 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72 , G11C2213/77 , H01L27/0688 , H01L27/101 , H01L27/2409 , H01L27/2418 , H01L27/2436 , H01L27/2454 , H01L45/08 , H01L45/1226 , H01L45/146 , H01L45/1616
摘要： A three-dimensional memory cell array of memory cells with two terminals having a variable resistive element is formed such that: one ends of memory cells adjacent in Z direction are connected to one of middle selection lines extending in Z direction aligned in X and Y directions; the other ends of the memory cells located at the same point in Z direction are connected to one of third selection lines aligned in Z direction; a two-dimensional array where selection transistors are aligned in X and Y directions is adjacent to the memory cell array in Z direction; gates of selection transistors adjacent in X direction, drains of selection transistors adjacent in Y direction and sources of selection transistors are connected to same first selection line, second selection line, and different middle selection lines, respectively; and first, second and third selection lines are connected to X, Y and Z decoders, respectively.
摘要翻译：具有两个具有可变电阻元件的端子的存储单元的三维存储单元阵列被形成为：在Z方向上相邻的存储单元的一端连接到沿Z方向延伸的中间选择线之一，在X和Y方向上对齐 ; 位于Z方向相同点的存储单元的另一端连接到在Z方向上排列的第三选择线之一; 选择晶体管在X和Y方向上排列的二维阵列与Z方向上的存储单元阵列相邻; 在X方向上相邻的选择晶体管的栅极，在Y方向相邻的选择晶体管的漏极和选择晶体管的源极分别连接到相同的第一选择线，第二选择线和不同的中间选择线; 并且第一，第二和第三选择线分别连接到X，Y和Z解码器。

10. 发明申请

US20100172170A1 VARIABLE RESISTIVE ELEMENT, MANUFACTURING METHOD FOR SAME, AND NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：可变电阻元件，其制造方法和非易失性半导体存储器件
公开(公告)号：US20100172170A1
公开(公告)日：2010-07-08
申请号：US12598642
申请日：2008-04-07
申请人： Yukio Tamai , Yasunari Hosoi , Nobuyoshi Awaya , Shigeo Ohnishi , Kazuya Ishihara , Hisashi Shima , Hiroyuki Akinaga , Fumiyoshi Takano
发明人： Yukio Tamai , Yasunari Hosoi , Nobuyoshi Awaya , Shigeo Ohnishi , Kazuya Ishihara , Hisashi Shima , Hiroyuki Akinaga , Fumiyoshi Takano
IPC分类号： G11C11/56 , H01L29/22 , H01L21/44
CPC分类号： G11C13/0011 , G11C11/5614 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/51 , G11C2213/56 , G11C2213/77 , H01L27/101 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： Provided is a variable resistive element which performs high speed and low power consumption operation. The variable resistive element comprises a metal oxide layer between first and second electrodes wherein electrical resistance between the first and second electrodes reversibly changes in accordance with application of electrical stress across the first and second electrodes. The metal oxide layer has a filament, which is a current path where the density of a current flowing between the first and second electrodes locally increases. A portion including at least the vicinity of an interface between the certain electrode, which is one or both of the first and second electrodes, and the filament, on an interface between the certain electrode and the metal oxide layer is provided with an interface oxide which is an oxide of at least one element included in the certain electrode and different from the oxide of the metal oxide layer.
摘要翻译：提供一种执行高速和低功耗操作的可变电阻元件。可变电阻元件包括在第一和第二电极之间的金属氧化物层，其中第一和第二电极之间的电阻根据跨越第一和第二电极的电应力的应用而可逆地改变。金属氧化物层具有灯丝，其是在第一和第二电极之间流动的电流的密度局部增加的电流路径。在特定电极和金属氧化物层之间的界面上至少包括作为第一和第二电极中的一个或两个的特定电极和灯丝之间的界面附近的部分设置有界面氧化物，其界面氧化物是包含在该特定电极中并且与金属氧化物层的氧化物不同的至少一种元素的氧化物。

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