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81. 发明授权

US06218242B1 Method for fabricating capacitors in semiconductor integrated circuit 有权
标题翻译：半导体集成电路制造电容器的方法
公开(公告)号：US06218242B1
公开(公告)日：2001-04-17
申请号：US09660622
申请日：2000-09-13
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L218242
CPC分类号： H01L28/91 , H01L27/10852
摘要： A capacitor is formed by providing a substrate, which has conductive structures with cap layer formed thereon. A first dielectric layer is formed over the substrate and the conductive structures. The first dielectric layer is patterned to form an opening to expose the substrate between the conductive structures and the sidewalls of the conductive structures. A conductive plug fills the opening. A second dielectric layer is formed over the first dielectric layer and the conductive plug. The second dielectric layer is patterned to form a narrow opening to expose the conductive plug. A conductive bar is formed to fill the narrow opening. The second dielectric layer is removed. A dielectric spacer is formed on the sidewall of the conductive bar. A conductive spacer is formed on the dielectric spacer. The conductive spacer has electric contact with the conductive plug. The dielectric spacer is removed by isotropic etching. Then, a conformal capacitor dielectric layer and an electrode conductive layer are sequentially formed over the substrate.
摘要翻译：通过提供具有形成在其上形成有帽层的导电结构的衬底来形成电容器。在衬底和导电结构之上形成第一电介质层。图案化第一电介质层以形成开口，以在导电结构和导电结构的侧壁之间露出衬底。导电塞填满开口。在第一介电层和导电插塞之上形成第二电介质层。图案化第二电介质层以形成窄的开口以暴露导电插塞。形成导电棒以填充狭窄的开口。去除第二介电层。介电隔离件形成在导电棒的侧壁上。在电介质间隔物上形成导电间隔物。导电间隔件与导电插头电接触。通过各向同性蚀刻去除电介质间隔物。然后，在衬底上顺序地形成保形电容器电介质层和电极导电层。

82. 发明授权

US6140178A Method to manufacture a capacitor with crown-shape using edge contact exposure 有权
标题翻译：使用边缘接触曝光制造具有冠状电容器的方法
公开(公告)号：US6140178A
公开(公告)日：2000-10-31
申请号：US287562
申请日：1999-04-06
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L28/91 , H01L27/10852 , H01L28/84
摘要： The present invention provides a method to manufacture a capacitor on a memory device. The capacitor formed on the memory device will only edge contacted with the related region, so a symmetrical formation of the capacitor to the related region of the memory device is not necessary, the manufacturing processes are therefore simplified to save the cost.
摘要翻译：本发明提供一种在存储器件上制造电容器的方法。形成在存储器件上的电容器将仅与相关区域边缘接触，因此电容器对存储器件的相关区域的对称形成是不必要的，因此制造工艺被简化以节省成本。

83. 发明授权

US6107211A Split polysilicon process in CMOS image integrated circuit 有权
标题翻译：在CMOS图像集成电路中分离多晶硅工艺
公开(公告)号：US6107211A
公开(公告)日：2000-08-22
申请号：US298965
申请日：1999-04-26
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/8238 , H01L21/00
CPC分类号： H01L21/823835
摘要： The invention discloses a split polycilicon process for forming poly gate and polycide gate with an almost equal height in a CMOS image integrated circuit fabricated on a substrate to reduce the sheet resistance of the poly gate electrode. First, a gate oxide layer is formed on a substrate, and then a polysilicon layer and a capped dielectric layer are sequentially deposited. Next, a poly gate is patterned by using a first photoresist layer, and then the capped dielectric layer and a portion of the polycilison layer are etched. Next, the first photoresist layer is removed. Thereafter, a silicide layer is deposited. Then, a polycide gate is patterned by using a second photoresist layer, and the silicide layer and the polysilicon layer is etched. Finally, the second photoresist layer is removed.
摘要翻译：本发明公开了一种用于在制造在衬底上的CMOS图像集成电路中形成具有几乎相同高度的多晶硅栅极和多晶硅栅极的分裂多晶硅工艺，以减小多晶硅栅极的薄层电阻。首先，在衬底上形成栅极氧化层，然后依次沉积多晶硅层和封端的电介质层。接下来，通过使用第一光致抗蚀剂层对多晶硅栅极进行构图，然后蚀刻封装的电介质层和一部分聚碳酸酯层。接下来，去除第一光致抗蚀剂层。此后，沉积硅化物层。然后，通过使用第二光致抗蚀剂层对多晶硅栅极进行构图，并且蚀刻硅化物层和多晶硅层。最后，去除第二光致抗蚀剂层。

84. 发明授权

US6082582A Automated carrier tube loading apparatus 失效
标题翻译：自动载体管装载装置
公开(公告)号：US6082582A
公开(公告)日：2000-07-04
申请号：US57298
申请日：1998-04-08
申请人： Chie-Wun Chiou , Horng-Huei Tseng
发明人： Chie-Wun Chiou , Horng-Huei Tseng
IPC分类号： B23Q7/00 , B23Q7/02 , B65G47/14 , H05K13/02
CPC分类号： B65G47/1471 , B23Q7/001 , B23Q7/02 , H05K13/021
摘要： A method and an apparatus for the automated loading of integrated circuit carrier tubes into a tube dispensing device in a predetermined, preferred orientation without the attention of a human operator are described. The method utilizes a roller equipped with tube cavities in its peripheral surface and rotates the roller in a clockwise direction for receiving tube carriers from a top hopper-shaped opening and discharging the tube carriers from a bottom opening by gravity.
摘要翻译：描述了一种将集成电路载体管自动加载到预先确定的优选方向的管分配装置中的方法和装置，而没有人操作者的注意。该方法利用在其周边表面上配备有管腔的辊，并且使辊沿顺时针方向旋转，以便从顶部料斗形开口接收管载体，并通过重力将管载体从底部开口排出。

85. 发明授权

US5940701A Method for forming a DRAM capacitor with four polysilicon pillars 失效
标题翻译：用四个多晶硅柱形成DRAM电容器的方法
公开(公告)号：US5940701A
公开(公告)日：1999-08-17
申请号：US984280
申请日：1997-12-03
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method for forming a capacitor of a dynamic random access memory cell is disclosed. The method includes patterning a first polysilicon layer (124) over a semiconductor substrate, wherein at least a portion of the first polysilicon layer is communicated to the substrate. An anti-oxidation layer (125) is formed on the first polysilicon layer, wherein a portion of the first polysilicon layer is exposed. The first polysilicon layer is then thermally oxidized using the anti-oxidation layer as a mask, thereby forming poly-oxide (128) on sidewalls and the exposed surface of the first polysilicon layer. A portion of the first polysilicon layer is etched using the poly-oxide as an etch mask, thereby forming a trench in the first polysilicon. Thereafter, a pair of inner dielectric spacers (130A) is formed on inner sidewalls of the trench, and a pair of outer dielectric spacers (130B) on outer sidewalls of the poly-oxide. A pair of inner polysilicon spacers (132A) is formed on inner sidewalls of the inner dielectric spacers, and a pair of outer polysilicon spacers (132B) on outer sidewalls of the outer dielectric spacers. The inner dielectric spacers, the dielectric spacers, and a portion of the first polysilicon layer are removed, whereby lifting off the pair of outer polysilicon spacers. Finally, a dielectric layer (136) is formed on the first polysilicon layer, and the pair of inner polysilicon spacers, and then a conductive layer (138) is then formed on the dielectric layer.
摘要翻译：公开了形成动态随机存取存储器单元的电容器的方法。该方法包括在半导体衬底上形成第一多晶硅层（124），其中第一多晶硅层的至少一部分与衬底连通。在第一多晶硅层上形成抗氧化层（125），其中露出第一多晶硅层的一部分。然后使用抗氧化层作为掩模将第一多晶硅层热氧化，从而在侧壁和第一多晶硅层的暴露表面上形成多晶氧化物（128）。使用多晶氧化物作为蚀刻掩模蚀刻第一多晶硅层的一部分，从而在第一多晶硅中形成沟槽。此后，在沟槽的内侧壁上形成一对内电介质间隔物（130A），在该多孔氧化物的外侧壁上形成一对外电介质间隔物（130B）。一对内部多晶硅间隔件（132A）形成在内部电介质间隔件的内侧壁上，以及一对在外部电介质间隔件的外侧壁上的外部多晶硅间隔件（132B）。去除内介电间隔物，电介质间隔物和第一多晶硅层的一部分，由此提起一对外多晶硅间隔物。最后，在第一多晶硅层上形成电介质层（136），然后在电介质层上形成一对内多晶硅间隔物，然后形成导电层（138）。

86. 发明授权

US5940298A Capacity loss control method for preventative maintenance in IC plant 失效
标题翻译：集成电路预防性维护的容量损失控制方法
公开(公告)号：US5940298A
公开(公告)日：1999-08-17
申请号：US852976
申请日：1997-05-07
申请人： Yirn-Sheng Pan , Horng-Huei Tseng , Chun-Yen Kuo , Jeng-Tyan Lin
发明人： Yirn-Sheng Pan , Horng-Huei Tseng , Chun-Yen Kuo , Jeng-Tyan Lin
IPC分类号： G05B19/418 , G06Q10/06 , G06F19/00
CPC分类号： G06Q10/06 , G05B19/4184 , G06Q10/0639 , Y02P90/14 , Y02P90/20
摘要： A process is provided for operating a manufacturing plant subsequent to preventative maintenance steps. The steps of the process are the following. Provide a data processing system having memory means for data storage. Provide central processing means for (a) accessing data from the memory means, (b) receiving data from data input means and (c) supplying data to the memory means. Provide Preventive Maintenance (PM) Duration (D) data to the data processing system. Calculate the effect of a PM schedule upon the efficiency of operation of the plant. Provide a new PM schedule to improve the efficiency of operation of the plant.
摘要翻译：提供了用于在预防性维护步骤之后操作制造工厂的过程。该过程的步骤如下。提供具有用于数据存储的存储装置的数据处理系统。提供用于（a）从存储装置访问数据的中央处理装置，（b）从数据输入装置接收数据，（c）向存储装置提供数据。向数据处理系统提供预防性维护（PM）持续时间（D）数据。计算PM时间表对工厂运行效率的影响。提供新的PM计划，以提高工厂的运行效率。

87. 发明授权

US5904561A Method for forming a barrier metal film with conformal step coverage in a semiconductor intergrated circuit 失效
标题翻译：在半导体集成电路中形成具有保形阶梯覆盖的阻挡金属膜的方法
公开(公告)号：US5904561A
公开(公告)日：1999-05-18
申请号：US777609
申请日：1996-12-31
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/768 , H01L21/28 , H01L21/3065
CPC分类号： H01L21/76843 , H01L21/76865
摘要： A method for forming a barrier metal film with conformal step coverage in a semiconductor integrated circuit includes forming a photoresist plug in a barrier metal lined contact or via hole. The barrier metal film has an overhang that narrows the opening to the contact or via hole. The barrier metal film is then etched using a fluorine based plasma etch process to remove the overhang. The photoresist plug is then removed using a oxygen based plasma etch process. The contact or via hole is then filled with tungsten to form a tungsten plug.
摘要翻译：在半导体集成电路中形成具有适形步骤覆盖的阻挡金属膜的方法包括在阻挡金属衬里的接触或通孔中形成光致抗蚀剂插塞。阻挡金属膜具有使接触孔或通孔开口变窄的突出端。然后使用氟基等离子体蚀刻工艺蚀刻阻挡金属膜以去除突出端。然后使用氧等离子体蚀刻工艺除去光致抗蚀剂插塞。然后用钨填充接触孔或通孔，形成钨丝塞。

88. 发明授权

US5811339A Method of fabricating deep submicron MOSFET with narrow gate length using thermal oxidation of polysilicon 失效
标题翻译：使用多晶硅热氧化制造窄栅长度的深亚微米MOSFET的方法
公开(公告)号：US5811339A
公开(公告)日：1998-09-22
申请号：US712148
申请日：1996-09-11
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/66583 , H01L21/28123 , H01L29/66537 , Y10S438/947
摘要： The present invention relates to forming a narrow gate MOSFET having a local ion implantation to reduce the junction capacitance. A polysilicon layer is formed over a semiconductor substrate. An opening is formed in the polysilicon layer by using patterning and etching. Subsequently, a thermal oxidation is performed to oxidize the polysilicon layer into a polysilicon-oxide layer that is expanded in volume relative to the polysilicon layer thereby narrowing said opening. Then an ion implantation is performed by using said polysilicon-oxide layer as a mask.
摘要翻译：本发明涉及形成具有局部离子注入的窄栅MOSFET以减小结电容。在半导体衬底上形成多晶硅层。通过图案化和蚀刻在多晶硅层中形成开口。随后，进行热氧化以将多晶硅层氧化成相对于多晶硅层膨胀体积的多晶硅 - 氧化物层，从而使所述开口变窄。然后通过使用所述多晶硅氧化物层作为掩模进行离子注入。

89. 发明授权

US5804481A Increased capacitor surface area via use of an oxide formation and removal procedure 失效
标题翻译：通过使用氧化物形成和去除程序增加电容器表面积
公开(公告)号：US5804481A
公开(公告)日：1998-09-08
申请号：US814138
申请日：1997-03-10
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , Y10S438/964
摘要： A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a saw-toothed topography for the top surface of a polysilicon storage node electrode. The saw-toothed topography is obtained by placing intrinsic HSG polysilicon spots on an underlying doped polysilicon layer. Thermal oxidation creates thick silicon oxide regions in areas of exposed doped polysilicon, while thinner silicon oxide regions form in areas in which the intrinsic HSG polysilicon spots are oxidized. Removal of both thick and thinner silicon oxide regions, creates the saw-toothed topography in the polysilicon storage node electrode, resulting in surface area, and capacitance increases.
摘要翻译：已经开发了用于高密度DRAM设计的STC结构的创建方法。该过程包括为多晶硅存储节点电极的顶表面创建锯齿状的形貌。通过将固有的HSG多晶硅斑点放置在下面的掺杂多晶硅层上来获得锯齿状的形貌。热氧化在暴露的掺杂多晶硅的区域中产生厚的氧化硅区域，而在内部HSG多晶硅斑点被氧化的区域中形成较薄的氧化硅区域。去除厚的和较薄的氧化硅区域，在多晶硅存储节点电极中产生锯齿状的形貌，导致表面积和电容增加。

90. 发明授权

US5753557A Bridge-free self aligned silicide process 失效
标题翻译：无桥自对准硅化物工艺
公开(公告)号：US5753557A
公开(公告)日：1998-05-19
申请号：US729737
申请日：1996-10-07
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/285 , H01L21/336 , H01L21/283
CPC分类号： H01L29/6659 , H01L21/28518 , H01L29/665
摘要： A method of forming a transistor having silicide contacts to shallow gate, source and drain regions 18 in a substrate 10 is disclosed. The transistor has an extended sidewall spacer that covers an outer top portion of the gate. The extended sidewall spacers of the invention extend the distance (leakage path) between the gate and the source/drain thereby reducing the leakage current. The transistor is provided having a gate electrode 12,14,16 and spaced lightly doped source and drain regions 18. A key part of the invention is that the gate insulating layer 16 is laterally etched forming a gate cap insulating layer 16A which only covers an inner central portion of the gate 14. Next, a dielectric layer 20 is formed over the lightly doped source and drain regions 18 and the gate electrode 12,14,16A . The dielectric layer 20 is then anisotropically etched forming extended sidewall spacers 20A which cover the outer top portion of the gate 14. Next, the gate cap insulating layer 16A is removed thereby exposing the top of the gate 14. A metal layer 22 is deposited over the lightly doped source and drain regions 18, the sidewall spacers 20A, and the gate 14. The substrate 10 is then heated thereby forming a metal silicide layer 22A on the lightly doped source and drain regions 18 and the gate 14. The metal layer 22A is then removed from the sidewall spacers 20A. The substrate 10 is implanted with impurity ions forming highly doped source and drain regions 26 and forming a doped gate region 27.
摘要翻译：公开了一种在衬底10中形成具有硅化物接触到浅栅极，源极和漏极区域18的晶体管的方法。晶体管具有覆盖栅极的外部顶部的延伸侧壁间隔物。本发明的延伸的侧壁间隔物延伸了栅极和源极/漏极之间的距离（泄漏路径），从而减小漏电流。晶体管被提供有栅电极12,14,16和间隔的轻掺杂源极和漏极区18.本发明的关键部分是栅极绝缘层16被横向蚀刻形成栅极绝缘层16A，其仅覆盖栅极14的内部中心部分。接下来，在轻掺杂的源极和漏极区域18以及栅极电极12,14,16A上形成电介质层20。然后各向异性地蚀刻电介质层20，形成覆盖栅极14的外顶部的延伸的侧壁间隔件20A。接下来，去除栅极帽绝缘层16A，从而暴露栅极14的顶部。金属层22沉积在轻掺杂源极和漏极区18，侧壁间隔物20A和栅极14.然后加热衬底10，从而在轻掺杂源极和漏极区18和栅极14上形成金属硅化物层22A。金属层22A 然后从侧壁间隔件20A中取出。衬底10注入形成高掺杂源极和漏极区26的杂质离子，并形成掺杂栅极区27。

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