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81. 发明授权

US06337834B1 Synchronous signal generation circuit 有权
标题翻译：同步信号发生电路
公开(公告)号：US06337834B1
公开(公告)日：2002-01-08
申请号：US09706842
申请日：2000-11-07
申请人： Katsuaki Isobe , Hironobu Akita , Satoshi Eto , Haruki Toda
发明人： Katsuaki Isobe , Hironobu Akita , Satoshi Eto , Haruki Toda
IPC分类号： G11C800
CPC分类号： G11C7/225 , G11C7/22 , G11C7/222
摘要： The present invention provides a synchronous signal generation circuit that can be operated with a high accuracy, at a high speed and with a low power consumption without being affected by the process dispersion. The synchronous signal generation circuit of the present invention comprises a real circuit including an input receiver, an off-chip driver, and a mirror-type synchronous circuit, and a dummy circuit for determining the delay time in the mirror-type synchronous circuit, the dummy circuit including an input receiver and an off-chip driver. In the dummy circuit, the input signal is supplied first to the off-chip driver and, then, to the input receiver so as to permit the signal between the off-chip driver and the input receiver to be a small amplitude signal. It follows that the real circuit and the dummy circuit are equal to each other in the signal levels in the input and output portions of each of the input receiver and the off-chip driver. The particular construction makes it possible to minimize the error in the delay time between the real circuit and the dummy circuit relative to the process dispersion so as to improve the synchronizing accuracy and, thus, to achieve a high speed I/O.
摘要翻译：本发明提供一种同步信号发生电路，其能够以高精度，高速度且低功耗地操作，而不受处理分散的影响。本发明的同步信号发生电路包括实际电路，其包括输入接收器，片外驱动器和反射镜型同步电路，以及用于确定镜式同步电路中的延迟时间的虚拟电路，虚拟电路包括输入接收器和片外驱动器。在虚拟电路中，首先将输入信号提供给片外驱动器，然后提供给输入接收器，以允许片外驱动器和输入接收器之间的信号为小振幅信号。因此，实际电路和虚拟电路在每个输入接收器和片外驱动器的输入和输出部分的信号电平中彼此相等。该特定结构使得可以将实际电路和虚拟电路之间相对于处理色散的延迟时间的误差最小化，从而提高同步精度，从而实现高速I / O。

82. 发明授权

US06317382B2 Semiconductor memory device 失效
公开(公告)号：US06317382B2
公开(公告)日：2001-11-13
申请号：US09812820
申请日：2001-03-21
申请人： Haruki Toda , Shozo Saito , Kaoru Tokushige
发明人： Haruki Toda , Shozo Saito , Kaoru Tokushige
IPC分类号： G11C800
CPC分类号： G11C7/1036 , G11C7/1018 , G11C7/1072 , G11C7/22 , G11C11/4076 , G11C11/4096 , G11C2207/107
摘要： A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for enterring them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number of cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic clock signal based on the control signal, and for controlling a specification operation executed by the specification circuit and the data I/O operation of the data I/O circuit, so that the memory access operations for the memory cell group are controlled.

83. 发明授权

US06265918B1 Clock signal processing circuit and semiconductor device in which a clock signal is processed in improved method 失效
标题翻译：时钟信号处理电路和其中以改进的方法处理时钟信号的半导体器件
公开(公告)号：US06265918B1
公开(公告)日：2001-07-24
申请号：US09389748
申请日：1999-09-07
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： H03L706
CPC分类号： G06F1/10 , G11C7/22 , H03K5/13 , H03K2005/00026 , H03K2005/00195 , H03L7/0812 , H03L7/089
摘要： A semiconductor device for inputting/outputting data in synchronism with a reference clock signal and an internal clock signal in each circuit. In this device, a variably delay section 104 delays a generated clock signal to output an internal clock signal, and a phase error-detecting section 107 detects a time difference between the internal clock signal and the reference clock signal, thereby controlling the delay amount of the variable delay section 104 to make the time difference substantially zero.
摘要翻译：一种用于在每个电路中与参考时钟信号和内部时钟信号同步地输入/输出数据的半导体器件。在该装置中，可变延迟部104延迟产生的时钟信号以输出内部时钟信号，相位误差检测部107检测内部时钟信号和基准时钟信号之间的时间差，由此控制延迟量可变延迟部分104使时差基本上为零。

84. 发明授权

US06192000B1 Semiconductor memory device having decreased layout area and method of manufacturing the same 失效
标题翻译：具有减小的布局面积的半导体存储器件及其制造方法
公开(公告)号：US06192000B1
公开(公告)日：2001-02-20
申请号：US09453038
申请日：1999-12-02
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C800
CPC分类号： G11C8/08 , G11C8/12
摘要： A word line driving circuit drives four word lines in response to a signal supplied from a main row decoder through a main word line and in response to a word line driving voltage supplied from a sub-row decoder. When the word line driving circuit is not selected by the main word line, a first reset circuit allows each word line to be short-circuited. When the word line driving circuit is selected by the main word line, second to fifth reset circuits allow the non-selected word line to bear a ground potential by using a signal of the selected word line.
摘要翻译：字线驱动电路响应于从主行解码器通过主字线提供的信号并且响应于从子行解码器提供的字线驱动电压来驱动四个字线。当字线驱动电路未被主字线选择时，第一复位电路允许每个字线短路。当字线驱动电路被主字线选择时，第二至第五复位电路允许未选字线通过使用所选字线的信号承受接地电位。

85. 发明授权

US06178518B1 Semiconductor memory system comprising synchronous DRAM and controller 失效
标题翻译：包括同步DRAM和控制器的半导体存储器系统
公开(公告)号：US06178518B1
公开(公告)日：2001-01-23
申请号：US09165692
申请日：1998-10-02
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G06F104
CPC分类号： G11C7/1093 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C7/225
摘要： A maximum flight time measuring circuit constituted by a first delay circuit for delaying a system clock and controlling its delay time in accordance with a strobe clock from DIMMs and a delayline register circuit for storing a delayed state in the delay circuit, and a second delay circuit are provided. Contents of the delayline register circuit are input to the second delay circuit, which is controlled to generate the same delay as that of the first delay circuit. The output of the second delay circuit is supplied as a data fetch signal to a control buffer for receiving read data DQ from the DIMMs.
摘要翻译：一种最大飞行时间测量电路，由第一延迟电路构成，用于根据来自DIMM的选通时钟延迟系统时钟并控制其延迟时间;以及延迟线寄存器电路，用于在延迟电路中存储延迟状态;以及第二延迟电路被提供。延迟线寄存器电路的内容被输入到第二延迟电路，其被控制以产生与第一延迟电路相同的延迟。第二延迟电路的输出作为数据提取信号提供给用于从DIMM接收读取数据DQ的控制缓冲器。

86. 发明授权

US6104649A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US6104649A
公开(公告)日：2000-08-15
申请号：US447190
申请日：1999-11-22
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C29/04 , G11C7/00 , G11C11/401 , G11C11/407 , G11C29/00
CPC分类号： G11C29/785 , G11C29/808 , G11C29/846
摘要： It is an object of this invention to provide a semiconductor memory device in which a failure can be efficiently remedied even for a larger number of bits. In a multi-bit memory capable of simultaneously exchanging a plurality of data upon reception of an address, square DQ lines (15c) commonly used for each I/O, a spare sense amplifier circuit (13c), a spare column switch (14c), a fuse box (20) for storing the address of a DQ line in which a failure has occurred, and fuse circuits (21-1, 21-2, . . . ) for storing an I/O to which the failure-DQ line belongs are arranged to remedy the failure for each I/O. Since only a memory cell belonging to one I/O where a failure has occurred is replaced, unnecessary replacement is not executed, and the memory cell can be efficiently remedied even for a larger number of bits.
摘要翻译：本发明的目的是提供一种半导体存储器件，其中即使对于较大数量的位也可有效地修复故障。在能够在接收到地址时同时交换多个数据的多位存储器中，通常用于每个I / O的方形DQ线（15c），备用读出放大器电路（13c），备用列开关（14c），用于存储其中发生故障的DQ线的地址的保险丝盒（20）和用于存储故障DQ的I / O的熔丝电路（21-1,21-2 ...）排列的行被排列以补救每个I / O的故障。由于只有属于发生故障的一个I / O的存储单元被替换，所以不执行不必要的替换，并且即使对于较大数量的位也能够有效地补救存储单元。

87. 发明授权

US6084453A Clock converting circuit 失效
标题翻译：时钟转换电路
公开(公告)号：US6084453A
公开(公告)日：2000-07-04
申请号：US105959
申请日：1998-06-29
申请人： Tsuneaki Fuse , Masahiro Kamoshida , Haruki Toda , Yukihito Oowaki
发明人： Tsuneaki Fuse , Masahiro Kamoshida , Haruki Toda , Yukihito Oowaki
IPC分类号： H03K5/04 , G06F1/06 , G11C11/407 , G11C11/4076 , H03K5/13 , H03K5/156 , H03K7/08
CPC分类号： H03K5/1565 , H03K5/133
摘要： A cycle measuring circuit 3 measures a cycle of an external clock signal, which is approximately m times a unit time. A number converting circuit 5 and a time converting circuit 7 cooperate, generating a pulse signal delayed by m/2.sup.K times the unit time, or by 1/2.sup.K times the cycle of the external clock signal. A logic circuit 8 generates an internal clock signal which rises in synchronism with the external clock signal and falls in synchronism with the pulse signal thus delayed. Hence, the internal clock signal has the same cycle as the external clock signal and has a desired duty ratio of (1/2.sup.K).times.100%.
摘要翻译：周期测量电路3测量大约是单位时间的m倍的外部时钟信号的周期。数字转换电路5和时间转换电路7协调，产生延迟了单位时间的m / 2K倍的脉冲信号，或者是外部时钟信号的周期的1 / 2K倍。逻辑电路8产生与外部时钟信号同步上升的内部时钟信号，并且与延迟的脉冲信号同步地下降。因此，内部时钟信号具有与外部时钟信号相同的周期，并且具有（1 / 2K）×100％的期望占空比。

88. 发明授权

US6034901A Clock control circuit 有权
标题翻译：时钟控制电路
公开(公告)号：US6034901A
公开(公告)日：2000-03-07
申请号：US327592
申请日：1999-06-08
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C11/407 , G06F1/10 , G06F13/42 , G11C7/22 , G11C19/00 , H03K5/135 , H03L7/00 , G11C7/00
CPC分类号： G11C7/225 , G11C7/22 , G11C7/222
摘要： An external clock signal CK is input to a buffer, which generates an internal clock signal CLK having a skew of D1 with respect to the external clock signal CK. The internal clock signal is input first to a delay circuit which has a delay time A, then to a delay array which provides a delay time D2, and finally to a delay circuit which has a delay time of D2. The delay circuit generates a corrected internal clock signal CK' which is synchronous with the external clock signal CK. The delay array is composed of delay units, each having a state-holding section. The state-holding section of any delay unit that has passed a forward pulse is set in a predetermined state. Once its state-holding section is set in the predetermined state, the delay unit provides a correct delay time of 2.times..DELTA..
摘要翻译：外部时钟信号CK被输入到缓冲器，其产生相对于外部时钟信号CK具有D1偏斜的内部时钟信号CLK。内部时钟信号首先输入到具有延迟时间A的延迟电路，然后输入到提供延迟时间D2的延迟阵列，最后输入延迟时间为D2的延迟电路。延迟电路产生与外部时钟信号CK同步的经校正的内部时钟信号CK'。延迟阵列由延迟单元组成，每个延迟单元具有状态保持部分。已经通过正向脉冲的任何延迟单元的状态保持部分被设置在预定状态。一旦其状态保持部分被设置在预定状态，则延迟单元提供2x DELTA的正确的延迟时间。

89. 发明授权

US5986968A Clock-synchronous semiconductor memory device and access method thereof 失效
标题翻译：时钟同步半导体存储器件及其访问方法
公开(公告)号：US5986968A
公开(公告)日：1999-11-16
申请号：US113570
申请日：1998-07-10
申请人： Haruki Toda , Hitoshi Kuyama
发明人： Haruki Toda , Hitoshi Kuyama
IPC分类号： G11C7/10 , G11C8/04 , G11C7/00
CPC分类号： G11C8/04 , G11C7/1045 , G11C7/1072
摘要： A clock-synchronous semiconductor memory device includes many memory cells arranged in matrix, a count section for counting the actual number of cycles of a continuous, externally-supplied basic clock signal, a control section for inputting a row enable control signal (/RE) and the column enable control signal (/CE) provided from an external device, other than the basic clock signal, for which the control signals are at a specified level, synchronized with the basic control signal, and for setting the initial address for data access of the memory cells, and a data I/O section for executing a data access operation for the address set by the control section. In the device, the output of data from the memory cells through the data I/O section is started after the setting of the initial address by the control sections and after a specified number of basic clock signals has been counted by the count section.
摘要翻译：时钟同步半导体存储器件包括以矩阵形式布置的许多存储器单元，用于对连续的外部供给的基本时钟信号的实际循环次数进行计数的计数部分，用于输入行使能控制信号（/ RE）的控制部分，以及与基本时钟信号不同的外部设备提供的与基本控制信号同步的指令级别的列使能控制信号（/ CE），并且用于设置用于数据访问的初始地址以及用于执行由控制部分设置的地址的数据访问操作的数据I / O部分。在设备中，通过控制部分设置初始地址之后，在计数部分计数了指定数量的基本时钟信号之后，通过数据I / O部分从存储器单元输出数据。

90. 发明授权

US5926436A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5926436A
公开(公告)日：1999-07-20
申请号：US17948
申请日：1998-02-03
申请人： Haruki Toda , Shozo Saito , Kaoru Tokushige
发明人： Haruki Toda , Shozo Saito , Kaoru Tokushige
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C7/22 , G11C8/04 , G11C11/407 , G11C11/41 , G11C11/413 , H01L27/10 , G11C8/00
CPC分类号： G11C7/1072 , G11C7/1018 , G11C7/22
摘要： A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for entering them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number of cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic clock signal based on the control signal, and for controlling a specification operation executed by the specification circuit and the data I/O operation of the data I/O circuit, so that the memory access operations for the memory cell group are controlled.
摘要翻译：半导体存储器件包括存储单元组，所述存储单元组包括排列成矩阵的多个存储器单元; 指定电路，用于依次指定存储器单元中由连续地址寻址的存储器单元，并将其输入激活状态; 用于对由指定电路指定的连续存储单元进行数据读出/写入操作（数据I / O操作）的数据输入/输出（I / O）电路，该控制基于读出/ 从外部部分提供的写入信号; 用于对从外部提供的基本时钟信号的周期数进行计数的计数器电路; 以及控制器，用于接收从外部部分提供的至少一个或多个指定信号，用于每个指定信号输出用于指定特定周期的控制信号作为开始周期，以对基本时钟信号的周期数进行计数，并且指示计数器电路基于控制信号对基本时钟信号的计数数进行计数，并且用于控制由指定电路执行的指定操作和数据I / O电路的数据I / O操作，使得控制存储单元组的存储器访问操作。

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