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1. 发明授权

US06337834B1 Synchronous signal generation circuit 有权
标题翻译：同步信号发生电路
公开(公告)号：US06337834B1
公开(公告)日：2002-01-08
申请号：US09706842
申请日：2000-11-07
申请人： Katsuaki Isobe , Hironobu Akita , Satoshi Eto , Haruki Toda
发明人： Katsuaki Isobe , Hironobu Akita , Satoshi Eto , Haruki Toda
IPC分类号： G11C800
CPC分类号： G11C7/225 , G11C7/22 , G11C7/222
摘要： The present invention provides a synchronous signal generation circuit that can be operated with a high accuracy, at a high speed and with a low power consumption without being affected by the process dispersion. The synchronous signal generation circuit of the present invention comprises a real circuit including an input receiver, an off-chip driver, and a mirror-type synchronous circuit, and a dummy circuit for determining the delay time in the mirror-type synchronous circuit, the dummy circuit including an input receiver and an off-chip driver. In the dummy circuit, the input signal is supplied first to the off-chip driver and, then, to the input receiver so as to permit the signal between the off-chip driver and the input receiver to be a small amplitude signal. It follows that the real circuit and the dummy circuit are equal to each other in the signal levels in the input and output portions of each of the input receiver and the off-chip driver. The particular construction makes it possible to minimize the error in the delay time between the real circuit and the dummy circuit relative to the process dispersion so as to improve the synchronizing accuracy and, thus, to achieve a high speed I/O.
摘要翻译：本发明提供一种同步信号发生电路，其能够以高精度，高速度且低功耗地操作，而不受处理分散的影响。本发明的同步信号发生电路包括实际电路，其包括输入接收器，片外驱动器和反射镜型同步电路，以及用于确定镜式同步电路中的延迟时间的虚拟电路，虚拟电路包括输入接收器和片外驱动器。在虚拟电路中，首先将输入信号提供给片外驱动器，然后提供给输入接收器，以允许片外驱动器和输入接收器之间的信号为小振幅信号。因此，实际电路和虚拟电路在每个输入接收器和片外驱动器的输入和输出部分的信号电平中彼此相等。该特定结构使得可以将实际电路和虚拟电路之间相对于处理色散的延迟时间的误差最小化，从而提高同步精度，从而实现高速I / O。

2. 发明授权

US06333658B1 Analog synchronization circuit 有权
标题翻译：模拟同步电路
公开(公告)号：US06333658B1
公开(公告)日：2001-12-25
申请号：US09707791
申请日：2000-11-08
申请人： Hironobu Akita , Satoshi Eto , Katsuaki Isobe , Masaharu Wada , Haruki Toda
发明人： Hironobu Akita , Satoshi Eto , Katsuaki Isobe , Masaharu Wada , Haruki Toda
IPC分类号： H03H1126
CPC分类号： H03K5/135
摘要： An analog synchronization circuit includes an input buffer which is supplied with an external clock signal, a delay monitor which is supplied with a clock signal output from the input buffer, an output buffer for outputting a clock signal synchronous with the external clock signal and two charge balance delay circuits. The two charge balance delay circuits are equivalent to delay lines in a mirror type delay locked loop. Each charge balance delay circuits operates once in two consecutive cycles of the external clock signal. The two charge balance delay circuits alternately operate and output signals of the charge balance delay circuits are supplied to the output buffer via an OR gate. First and second capacitors are provided in each charge balance delay circuits. A first current source circuit charges the first capacitor for a time equivalent to a delay time of a forward pulse. The second capacitor is charged by a second current source circuit. A comparator compares charge voltages of the first and second capacitors with each other and generates a timing signal when both charge voltages coincide with each other.
摘要翻译：模拟同步电路包括被提供有外部时钟信号的输入缓冲器，被提供有从输入缓冲器输出的时钟信号的延迟监视器，用于输出与外部时钟信号同步的时钟信号的输出缓冲器和两个充电平衡延迟电路。两个电荷平衡延迟电路等效于镜像延迟锁定环路中的延迟线。每个电荷平衡延迟电路在外部时钟信号的两个连续周期中运行一次。两个电荷平衡延迟电路交替工作，并且电荷平衡延迟电路的输出信号通过或门提供给输出缓冲器。在每个电荷平衡延迟电路中提供第一和第二电容器。第一电流源电路对第一电容器充电等于正向脉冲的延迟时间的时间。第二电容器由第二电流源电路充电。比较器将第一和第二电容器的充电电压彼此进行比较，并且当两个充电电压彼此一致时产生定时信号。

3. 发明授权

US06339345B1 Semiconductor device equipped with output circuit adjusting duration of high and low levels 有权
标题翻译：半导体器件配备有输出电路调节持续时间的高低电平
公开(公告)号：US06339345B1
公开(公告)日：2002-01-15
申请号：US09696048
申请日：2000-10-26
申请人： Satoshi Eto , Hironobu Akita , Katsuaki Isobe
发明人： Satoshi Eto , Hironobu Akita , Katsuaki Isobe
IPC分类号： H03L700
CPC分类号： G11C7/1066 , G11C7/1072 , G11C7/222 , G11C2207/2254 , H03K5/135 , H03K19/00384 , H03L7/00
摘要： In an output circuit 10, a latch circuit 11, a phase difference controlled circuit 12 and an output buffer circuit 13 are cascaded and a DATA is clocked into the latch circuit 11. A replica circuit 20 is a down-scaled version of a layout pattern of the output circuit 10, comprises circuits 21 to 23 corresponding to the circuits 11, 12 and 13, and a CLK is provided through a delay circuit 5 and a divide-by-2 frequency divider 16 to the data input of the latch circuit 21 as a data. The output of the replica circuit 20 is provided through a dummy load circuit 24 and a low pass filter 25 to a comparator 26, the output thereof is compared with a reference voltage Vref to generate count-up or count-down pulses. The pulses are counted by an up-down counter 27 whose count is provided to the phase difference controlled circuit 12 and its replica 22 to reduce the phase difference between rising and falling edges of the output signal of the output buffer circuit 23.
摘要翻译：在输出电路10中，锁存电路11，相位差控制电路12和输出缓冲器电路13级联，并且DATA被锁定到锁存电路11中。复制电路20是布局模式的缩小版本输出电路10包括对应于电路11,12和13的电路21至23，并且通过延迟电路5和分频2分频器16将CLK提供给锁存电路21的数据输入作为数据。复制电路20的输出通过虚拟负载电路24和低通滤波器25提供给比较器26，其输出与参考电压Vref进行比较，以产生递增计数或递减计数脉冲。脉冲由计数器27计数，该计数器的计数被提供给相位差控制电路12及其副本22，以减小输出缓冲电路23的输出信号的上升沿和下降沿之间的相位差。

4. 发明授权

US06313674B1 Synchronizing circuit for generating internal signal synchronized to external signal 有权
标题翻译：同步电路，用于产生与外部信号同步的内部信号
公开(公告)号：US06313674B1
公开(公告)日：2001-11-06
申请号：US09641139
申请日：2000-08-16
申请人： Hironobu Akita , Satoshi Eto , Katsuaki Isobe
发明人： Hironobu Akita , Satoshi Eto , Katsuaki Isobe
IPC分类号： H03L706
CPC分类号： G11C7/222 , G06F1/10 , G11C7/22 , H03K5/135 , H03L7/0812
摘要： A variable delay line outputs a clock signal advanced in phase by a time corresponding to a sum tH+tL of a time tH required to output high level data from an OCD circuit and a time tL required to output low level data from the OCD circuit. A replica circuit for outputting low level data has the same configuration as a circuit portion of the OCD circuit through which low level data passes. The replica circuit outputs a start signal SSH for outputting high level data from the OCD circuit. Another replica circuit for outputting high level data has the same configuration as a circuit portion of the OCD circuit through which high level data passes. The replica circuit outputs a start signal SSL for outputting low level data from the OCD circuit.
摘要翻译：可变延迟线输出相位提前的时钟信号与从OCD电路输出高电平数据所需的时间tH的和tH + tL和从OCD电路输出低电平数据所需的时间tL的时间。用于输出低电平数据的复制电路具有与低电平数据通过的OCD电路的电路部分相同的配置。复制电路输出用于从OCD电路输出高电平数据的启动信号SSH。用于输出高电平数据的另一复制电路具有与高电平数据通过的OCD电路的电路部分相同的配置。复制电路输出用于从OCD电路输出低电平数据的起始信号SSL。

5. 发明授权

US06753695B2 Semiconductor integrated circuit device and pulse width changing circuit 失效
标题翻译：半导体集成电路器件和脉冲宽度变化电路
公开(公告)号：US06753695B2
公开(公告)日：2004-06-22
申请号：US10104069
申请日：2002-03-25
申请人： Haruki Toda , Kenji Tsuchida , Satoshi Eto , Kuninori Kawabata
发明人： Haruki Toda , Kenji Tsuchida , Satoshi Eto , Kuninori Kawabata
IPC分类号： H03K3017
CPC分类号： H03K5/13 , H03K5/06 , H03K5/08
摘要： A semiconductor integrated circuit device comprises a plurality of MIS transistors, and an integrated circuit unit including logic gate circuits configured by a combination of the plurality of MIS transistors. Each of the MIS transistors has a gate including a circuit element represented by an equivalent circuit in which a capacitance and resistance are parallel-connected.
摘要翻译：半导体集成电路器件包括多个MIS晶体管，以及集成电路单元，其包括由多个MIS晶体管的组合构成的逻辑门电路。每个MIS晶体管具有包括由电容和电阻并联连接的等效电路表示的电路元件的栅极。

6. 发明授权

US06549154B2 Digital-to-analog converter and synchronous circuit using the converter 有权
公开(公告)号：US06549154B2
公开(公告)日：2003-04-15
申请号：US10007694
申请日：2001-12-10
申请人： Katsuaki Isobe , Satoshi Eto
发明人： Katsuaki Isobe , Satoshi Eto
IPC分类号： H03M180
CPC分类号： H03L7/093 , H03L7/0812
摘要： A digital-to-analog converter circuit includes a converter configured to convert digital signals of bit n (n=0, 1, 2, . . . , N) to voltage values, a plurality of amplifiers configured to output currents having different values in accordance with the voltage values, and an adder configured to assigning weights to the currents and adding the currents together in response to the digital signal of bit n.

7. 发明授权

US08692926B2 Focus adjustment based on indicator of randomness of pixel values 有权
标题翻译：基于像素值随机性指标的焦点调整
公开(公告)号：US08692926B2
公开(公告)日：2014-04-08
申请号：US12938994
申请日：2010-11-03
申请人： Satoshi Eto , Senshu Igarashi
发明人： Satoshi Eto , Senshu Igarashi
IPC分类号： H04N5/232 , G03B13/00
CPC分类号： H04N5/23212 , H04N5/2353
摘要： A circuit for auto-focus adjustment includes a calculating unit configured to calculate an indicator of randomness of pixel values in a captured image, a direction determining unit configured to compare a first value of the indicator calculated by the calculating unit in a preceding focus adjustment process with a second value of the indicator calculated by the calculating unit after the calculation of the first value, thereby to determine a direction of focus shift in response to a result of the comparison, and a control unit configured to start a focus adjustment process by which a focus position is first moved in the direction of focus shift determined by the direction determining unit.
摘要翻译：一种用于自动对焦调整的电路包括：计算单元，被配置为计算拍摄图像中的像素值的随机性的指标;方向确定单元，被配置为将由所述计算单元计算出的指标的第一值与先前的焦点调整处理在计算第一值之后由计算单元计算出的指示符的第二值，从而根据比较结果确定焦点偏移的方向，以及控制单元，其被配置为开始焦点调整处理，通过该调整处理，首先在由方向确定单元确定的聚焦偏移的方向上移动聚焦位置。

8. 发明申请

US20100220540A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF DRIVING NON-SELECTED WORD LINES TO FIRST AND SECOND POTENTIALS 审中-公开
公开(公告)号：US20100220540A1
公开(公告)日：2010-09-02
申请号：US12718808
申请日：2010-03-05
申请人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
发明人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C8/08 , G11C8/12 , G11C11/4074 , G11C11/4085 , G11C2207/2227
摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

9. 发明授权

US07706209B2 Semiconductor memory device capable of driving non-selected word lines to a variable negative potential based on a bank access operation 失效
标题翻译：能够基于银行存取操作将未选字线驱动到可变负电位的半导体存储器件
公开(公告)号：US07706209B2
公开(公告)日：2010-04-27
申请号：US11313963
申请日：2005-12-22
申请人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
发明人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
IPC分类号： G11C8/08
CPC分类号： G11C5/147 , G11C8/08 , G11C8/12 , G11C11/4074 , G11C11/4085 , G11C2207/2227
摘要： A semiconductor device, including a word line driver for driving a word line connected to a memory cell in a memory cell array and for resetting the word line when the memory cell changes from an activated to a standby state. The reset level of the word line driver is set when resetting of the word line is performed, and may be switched between first and second potentials. A word line reset level generating circuit varies the amount of negative potential current supply in accordance with memory cell array operating conditions. The semiconductor device includes a plurality of power source circuits, each having an oscillation circuit and a capacitor, for driving the capacitor via an oscillation signal outputted by the oscillation circuit. At least some power source circuits share a common oscillation circuit, and different capacitors are driven via the common oscillation signal.
摘要翻译：一种半导体器件，包括用于驱动连接到存储单元阵列中的存储单元的字线的字线驱动器，以及当存储器单元从激活状态变为待机状态时重新设定字线。当执行字线的复位时，字线驱动器的复位电平被设置，并且可以在第一和第二电位之间切换。字线复位电平发生电路根据存储单元阵列工作条件改变负电位电流供给量。半导体器件包括多个电源电路，每个电源电路具有振荡电路和电容器，用于经由振荡电路输出的振荡信号来驱动电容器。至少一些电源电路共用一个共同的振荡电路，而不同的电容通过公共振荡信号驱动。

10. 发明授权

US07630268B2 Dynamic semiconductor memory reducing the frequency of occurrence of refresh command request and refresh control method thereof 失效
标题翻译：动态半导体存储器降低刷新命令请求的发生频率及其刷新控制方法
公开(公告)号：US07630268B2
公开(公告)日：2009-12-08
申请号：US11450472
申请日：2006-06-12
申请人： Satoshi Eto
发明人： Satoshi Eto
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40618
摘要： A dynamic semiconductor memory has a plurality of memory blocks and a memory core. Each of the memory blocks has a sense amplifier, and the memory core is formed from memory cells located at intersections between a plurality of word lines and a plurality of bit lines connected to the sense amplifier. The memory blocks are sequentially refreshed by selecting each of the word lines and by simultaneously activating the memory cells connected to the selected word line by the sense amplifier. The dynamic semiconductor memory has a first refresh counter which outputs a first internal refresh candidate address, and a second refresh counter which outputs a second internal refresh candidate address that is different from the first internal refresh candidate address. When an externally accessed address coincides with the first internal refresh candidate address, a refresh operation is performed starting from the second internal refresh candidate address.
摘要翻译：动态半导体存储器具有多个存储器块和存储器核。每个存储块具有读出放大器，并且存储器核心由位于多个字线与连接到读出放大器的多个位线之间的交点处的存储器单元形成。通过选择每个字线并且通过感测放大器同时激活连接到所选择的字线的存储器单元来顺序刷新存储器块。动态半导体存储器具有输出第一内部刷新候补地址的第一刷新计数器和输出与第一内部刷新候补地址不同的第二内部刷新候补地址的第二刷新计数器。当外部访问的地址与第一内部刷新候选地址一致时，从第二内部刷新候选地址开始执行刷新操作。

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