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81. 发明授权

US06376369B1 Robust pressure aluminum fill process 失效
标题翻译：坚固的压力铝填充过程
公开(公告)号：US06376369B1
公开(公告)日：2002-04-23
申请号：US09022568
申请日：1998-02-12
申请人： Trung T. Doan
发明人： Trung T. Doan
IPC分类号： H01L214763
CPC分类号： H01L21/76882 , H01L21/28556 , H01L21/76841 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A method of metallization for a semiconductor channel, trench, or via with a high aspect ratio lined with a barrier metal layer. The channel, trench, or via is situated in a semiconductor substrate and the barrier metal layer has deposited thereon two metal layers, the first of which has a lower melting point by at least 10° C. than that of the second. A low temperature, high pressure process is used to alloy together the two uppermost metal layers and bond them to a barrier metal, and thereby substantially fill up the channel, trench, or via without leaving a void therein and without breaching the barrier layer in a pitting phenomenon.
摘要翻译：用于半导体沟槽，沟槽或通孔的金属化方法，其具有衬有阻挡金属层的高纵横比。通道，沟槽或通孔位于半导体衬底中，并且阻挡金属层在其上沉积有两个金属层，其中第一层具有比第二层更低的熔点至少10℃。使用低温高压工艺将两个最上层金属层合并在一起，并将它们结合到阻挡金属上，从而基本上填充沟道，沟槽或通孔，而不会在其中留下空隙，而不会在点蚀现象

82. 发明授权

US06207571B1 Self-aligned contact formation for semiconductor devices 有权
标题翻译：用于半导体器件的自对准接触形成
公开(公告)号：US06207571B1
公开(公告)日：2001-03-27
申请号：US09515804
申请日：2000-02-29
申请人： Werner Juengling , Kirk Prall , Trung T. Doan , Guy T. Blalock , David Dickerson , David S. Becker
发明人： Werner Juengling , Kirk Prall , Trung T. Doan , Guy T. Blalock , David Dickerson , David S. Becker
IPC分类号： H01L2100
CPC分类号： H01L27/10894 , H01L21/316 , H01L21/31625 , H01L21/76897
摘要： In accordance with the present invention, there is provided a method for fabricating a contact on an integrated circuit, such as a DRAM. The method includes the following steps. A gate stack is formed on the integrated circuit. A spacer is formed on sidewalls of the gate stack. An insulating film is formed on the integrated circuit. The insulating film is planarized. Finally, a gate contact opening is formed through the planarized insulating film. In one embodiment, the gate contact opening is formed by removing the insulator, spacer and insulating film by etching. In this embodiment, the insulator, spacer and insulating film are etched at substantially similar rates. As a result, the integrated circuit is tolerant of mask misalignments, and does not over-etch field oxide or create silicon nitride slivers. In another embodiment, the planarizing step is performed with chemical mechanical planarization to form a substantially flat topography on the surface of the integrated circuit. Thus, the present invention does not require lithography equipment with a relatively large field of depth. In yet a third embodiment, the method may comprise additional steps, including forming additional dielectric on the integrated circuit. Then, gate and bitline contact openings are formed through the additional dielectric. Finally, gate and bitline contacts are formed in self-alignment to the gate stacks. This embodiment may be implemented by forming the gate and bitline contact openings with an etch that removes the additional dielectric, but does not substantially remove the spacer. As a result, the bitline contact cannot be inadvertently connected to a gate stack that functions as a wordline. This connection might disable the integrated circuit.
摘要翻译：根据本发明，提供了一种用于在诸如DRAM的集成电路上制造接触的方法。该方法包括以下步骤。在集成电路上形成栅极堆叠。在栅叠层的侧壁上形成间隔物。在集成电路上形成绝缘膜。绝缘膜平坦化。最后，通过平坦化绝缘膜形成栅极接触开口。在一个实施例中，通过蚀刻去除绝缘体，间隔物和绝缘膜来形成栅极接触开口。在该实施例中，以基本相似的速率蚀刻绝缘体，间隔物和绝缘膜。因此，集成电路容忍掩模未对准，并且不会过度蚀刻场氧化物或产生氮化硅条。在另一个实施例中，平面化步骤通过化学机械平面化进行，以在集成电路的表面上形成基本平坦的形貌。因此，本发明不需要具有相当大的深度场的光刻设备。在第三个实施例中，该方法可以包括额外的步骤，包括在集成电路上形成附加电介质。然后，通过附加电介质形成栅极和位线接触开口。最后，栅极和位线触点形成为与栅极堆叠自对准。该实施例可以通过用蚀刻去除附加电介质但不基本上去除间隔物的栅极和位线接触开口来实现。因此，位线接触不能无意中连接到用作字线的栅极堆叠。此连接可能会禁用集成电路。

83. 发明授权

US6057581A Self-aligned contacts 有权
标题翻译：自对准接触
公开(公告)号：US6057581A
公开(公告)日：2000-05-02
申请号：US239577
申请日：1999-01-28
申请人： Trung T. Doan
发明人： Trung T. Doan
IPC分类号： H01L21/60 , H01L29/76
CPC分类号： H01L21/76897 , Y10S257/90
摘要： A process of forming a self aligned contact on a surface of a wafer having one or more gate structures and a contact region adjacent the gate structures. The gate structures are isolated from the contact region by one or more spacers having predetermined thicknesses. The process comprises the steps of depositing a conformal etch stop layer over the gate structures and contact region, depositing a sacrificial layer over the etch stop layer, selectively removing a portion of the sacrificial layer to expose a portion of the etch stop layer adjacent the contact region and removing the etch stop layer to expose contact region. The etch stop layer protects spacers from damage resulting from selective etch of the sacrificial layer. In one preferred embodiment, the etch stop layer has a substantially uniform thickness and may be removed by a timed etch.
摘要翻译：在具有一个或多个栅极结构和邻近栅极结构的接触区域的晶片的表面上形成自对准接触的工艺。栅极结构通过一个或多个具有预定厚度的间隔物与接触区域隔离。该方法包括以下步骤：在栅极结构和接触区域上沉积保形蚀刻停止层，在蚀刻停止层上沉积牺牲层，选择性地去除牺牲层的一部分以暴露邻近接触部分的蚀刻停止层的一部分并且去除蚀刻停止层以暴露接触区域。蚀刻停止层保护隔离物免受对牺牲层的选择性蚀刻的损害。在一个优选实施例中，蚀刻停止层具有基本均匀的厚度，并且可以通过定时蚀刻去除。

84. 发明授权

US5849628A Method of producing rough polysilicon by the use of pulsed plasma chemical vapor deposition and products produced by same 失效
公开(公告)号：US5849628A
公开(公告)日：1998-12-15
申请号：US762544
申请日：1996-12-09
申请人： Gurtej S. Sandhu , Trung T. Doan
发明人： Gurtej S. Sandhu , Trung T. Doan
IPC分类号： C23C16/24 , C23C16/515 , H01L21/02 , H01L21/285 , H01L21/20
CPC分类号： H01L28/82 , C23C16/24 , C23C16/515 , H01L21/28525 , Y10S438/964
摘要： A method for depositing a rough polysilicon film on a substrate is disclosed. The method includes introducing the reactant gases argon and silane into a deposition chamber and enabling and disabling a plasma at various times during the deposition process.

85. 发明授权

US5723382A Method of making a low-resistance contact to silicon having a titanium silicide interface, an amorphous titanium nitride barrier layer and a conductive plug 失效
标题翻译：对具有钛硅化物界面的硅进行低电阻接触的方法，非晶氮化钛阻挡层和导电插塞
公开(公告)号：US5723382A
公开(公告)日：1998-03-03
申请号：US509708
申请日：1995-07-31
申请人： Gurtej S. Sandhu , Trung T. Doan , Tyler A. Lowrey
发明人： Gurtej S. Sandhu , Trung T. Doan , Tyler A. Lowrey
IPC分类号： C23C16/34 , H01L21/285 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76855 , C23C16/34 , H01L21/28568 , H01L21/76843
摘要： This invention constitutes a contact structure incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe.sub.2).sub.4, as the precursor. The contact structure is fabricated by etching a contact opening through an dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening. Chemical vapor deposition of polycrystalline silicon, or of metal, such as tungsten, follows, and proceeds until the contact opening is completely filled with either polycrystalline silicon or metal.
摘要翻译：本发明构成了采用利用四 - 二烷基酰胺基钛，Ti（NMe 2）4作为前体的低压化学气相沉积（LPCVD）形成的无定形氮化钛阻挡层的接触结构。通过将通过电介质层的接触开口蚀刻到要进行电接触的扩散区域来制造接触结构。钛金属沉积在晶片的表面上，使得扩散区域的暴露表面完全被金属层覆盖。钛金属层的至少一部分最终被转化为硅化钛，从而在扩散区的表面提供优异的导电界面。然后使用LPCVD工艺沉积氮化钛阻挡层，涂覆接触开口的壁和底板。多晶硅或金属如钨的化学气相沉积随后进行，直到接触开口完全充满多晶硅或金属。

86. 发明授权

US5585282A Process for forming a raised portion on a projecting contact for electrical testing of a semiconductor 失效
标题翻译：用于在半导体的电气测试的突出接触件上形成凸起部分的工艺
公开(公告)号：US5585282A
公开(公告)日：1996-12-17
申请号：US406637
申请日：1995-03-20
申请人： Alan G. Wood , Trung T. Doan , Warren M. Farnworth , Tim J. Corbett
发明人： Alan G. Wood , Trung T. Doan , Warren M. Farnworth , Tim J. Corbett
IPC分类号： G01R1/04 , G01R1/067 , G01R3/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L21/68 , H01L23/13 , H01L23/498 , H05K3/00 , H05K3/40 , H05K3/42 , H01L21/28 , H01L21/308
CPC分类号： H05K3/4007 , G01R1/0466 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/80 , G01R3/00 , H01L2224/13012 , H01L2224/13019 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/81192 , H01L2224/81345 , H01L2224/83192 , H01L2225/06562 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H05K3/0058 , H05K3/0067 , H05K3/423
摘要： A process for forming die contacting substrate for establishing ohmic contact with the die is formed with raised portions on contact members. The raised portions are dimensioned so that a compression force applied to the die against the substrate results in a limited penetration of the contact member into the bondpads. In the preferred embodiment, the substrate is formed of semiconductor material, with the raised portions being formed by etching. The arrangement may be used for establishing temporary electrical contact with a burn-in oven and with a discrete die tester. This permits the die to be characterized prior to assembly, so that the die may then be transferred in an unpackaged form. A Z-axis anisotropic conductive interconnect material may be interposed between the die attachment surface and the die.
摘要翻译：用于与模具建立欧姆接触的用于形成模具接触衬底的方法在接触构件上形成有凸起部分。凸起部分的尺寸被设计成使得对模具施加到基板上的压缩力导致接触构件有限地渗透到粘合垫中。在优选实施例中，衬底由半导体材料形成，凸起部分通过蚀刻形成。该装置可用于与老化烘箱和分立模具测试仪建立临时电接触。这允许在组装之前对模具进行表征，从而可以以未包装的形式转移模具。 Z轴各向异性导电互连材料可以插入在模具附接表面和模具之间。

87. 发明授权

US5514245A Method for chemical planarization (CMP) of a semiconductor wafer to provide a planar surface free of microscratches 失效
标题翻译：半导体晶片的化学机械平面化（CMP）的方法，以提供没有微观尺度的平面
公开(公告)号：US5514245A
公开(公告)日：1996-05-07
申请号：US430276
申请日：1995-04-28
申请人： Trung T. Doan , Malcolm Grief , Laurence D. Schultz
发明人： Trung T. Doan , Malcolm Grief , Laurence D. Schultz
IPC分类号： B24B37/04 , C30B33/00 , H01L21/306 , H01L21/3105
CPC分类号： H01L21/31053 , B24B37/04 , C30B33/00 , Y10S438/959
摘要： A method of chemically-mechanically planarizing (CMP) a dielectric layer formed on semiconductor wafer includes planarizing the dielectric layer with a polishing pad formed of a hard low compressibility pad material, and then polishing the dielectric layer with a polishing pad formed of a soft compressible pad material to remove micro-scratches formed during the planarization step. During the planarization step, the hard low compressibility pad material does not deform into the surface of the dielectric layer and the dielectric layer is planarized along a single contact plane. A loading effect in which the a material compresses and produces an irregular surface is thus eliminated.
摘要翻译：将形成在半导体晶片上的电介质层进行化学机械平面化（CMP）的方法包括用由硬的低压缩性垫材料形成的抛光垫对介电层进行平面化，然后用由软压缩材料形成的抛光垫垫材料以去除在平坦化步骤期间形成的微划痕。在平坦化步骤期间，硬的低压缩性垫材料不会变形到电介质层的表面，并且电介质层沿着单个接触平面平坦化。因此消除了材料压缩并产生不规则表面的负载效应。

88. 发明授权

US5395801A Chemical-mechanical polishing processes of planarizing insulating layers 失效
标题翻译：平面化绝缘层的化学机械抛光工艺
公开(公告)号：US5395801A
公开(公告)日：1995-03-07
申请号：US130117
申请日：1993-09-29
申请人： Trung T. Doan , Scott Meikle
发明人： Trung T. Doan , Scott Meikle
IPC分类号： B24B1/00 , H01L21/304 , H01L21/3105 , H01L21/768 , H01L21/302 , H01L21/463
CPC分类号： H01L21/31053 , H01L21/76819
摘要： A semiconductor processing method of providing and planarizing an insulating layer on a semiconductor wafer includes the following sequential steps: a) providing a conformal layer of insulating material to a first thickness over a semiconductor wafer having non-planar topography; b) providing a CMP polishing protective layer over the conformal layer to a second thickness, the protective layer being of different composition than the conformal layer; and c) chemical-mechanical polishing the protective layer and conformal layer in a single CMP step using a single CMP slurry and under conditions which in combination with the slurry remove the conformal layer material at a faster rate than the protective layer material, the protective layer upon outward exposure of conformal layer material in high topographical areas restricting material removal from low topographical areas during such chemical-mechanical polishing. Alternately, the protective layer and conformal layer are CMPed in at least two steps using first and second respective CMP slurries. The first CMP step and slurry remove outermost portions of the protective layer in a manner which is substantially selective to the underlying conformal layer to outwardly expose conformal layer material in high topographical areas. The second CMP step and slurry remove the conformal layer material at a faster rate than the protective layer material. The protective layer upon outward exposure of conformal layer material in high topographical areas restricts material removal from low topographical areas during such second CMP step.
摘要翻译：在半导体晶片上提供和平坦化绝缘层的半导体处理方法包括以下顺序步骤：a）在具有非平面形貌的半导体晶片上提供具有第一厚度的绝缘材料的共形层; b）在所述共形层上提供CMP抛光保护层至第二厚度，所述保护层具有不同于所述共形层的组成; 和c）在单个CMP步骤中使用单个CMP浆料在保护层和共形层上进行化学机械抛光，在与浆料组合的情况下，以比保护层材料更快的速率去除保形层材料，保护层在保护层材料在高地形区域中向外暴露时，限制在这种化学机械抛光期间从低地形区域移除材料。或者，使用第一和第二各自的CMP浆料，至少两个步骤将保护层和共形层CMP化。第一CMP步骤和浆料以对下面的共形层基本上选择性的方式去除保护层的最外部分，以在高地形区域中向外暴露共形层材料。第二CMP步骤和浆料以比保护层材料更快的速率除去保形层材料。保护层在保形层材料向外暴露于高地形区域时，限制了在这样的第二CMP步骤期间从低地形区域的材料去除。

89. 发明授权

US5346585A Use of a faceted etch process to eliminate stringers 失效
标题翻译：使用刻面蚀刻工艺消除桁条
公开(公告)号：US5346585A
公开(公告)日：1994-09-13
申请号：US49274
申请日：1993-04-20
申请人： Trung T. Doan , Guy T. Blalock
发明人： Trung T. Doan , Guy T. Blalock
IPC分类号： H01L21/311 , H01L21/00
CPC分类号： H01L21/31116
摘要： A process to create a faceted (prograde) profile for an integrated circuit, in which the top corners of a layer disposed over a feature are preferentially etched, thereby creating slopes. The profile which results from the deposit of subsequent layers is more easily etched as a result of the contour imparted by the faceted edges. Since the subsequent layers are placed in the "line of sight" of the etch plasma, there are significantly fewer "stringers."
摘要翻译：为集成电路创建刻面（前进）轮廓的过程，其中优先蚀刻设置在特征上的层的顶角，从而产生斜面。由于由分面边缘赋予的轮廓，更容易地蚀刻由后续层的沉积产生的轮廓。由于随后的层被放置在蚀刻等离子体的“视线”中，所以显着减少了“桁条”。

90. 发明授权

US5254499A Method of depositing high density titanium nitride films on semiconductor wafers 失效
标题翻译：在半导体晶片上沉积高密度氮化钛膜的方法
公开(公告)号：US5254499A
公开(公告)日：1993-10-19
申请号：US914748
申请日：1992-07-14
申请人： Gurtej S. Sandhu , Trung T. Doan , Scott G. Meikle
发明人： Gurtej S. Sandhu , Trung T. Doan , Scott G. Meikle
IPC分类号： H01L21/285 , H01L21/283
CPC分类号： H01L21/28512
摘要： Disclosed is a chemical vapor deposition method of providing a conformal layer of TiN atop a semiconductor wafer in a manner which increases density and reduces etch rate of the TiN layer. The method comprises: a) positioning a wafer within a chemical vapor deposition reactor; b) heating the positioned wafer to a selected processing temperature of from about 200.degree. C. to about 600.degree. C.; c) injecting selected quantities of a gaseous titanium organometallic precursor of the formula Ti(NR.sub.2).sub.4, where R is selected from the group consisting of H and a carbon containing radical; gaseous ammonia; and a carrier gas to within the reactor having the positioned preheated wafer therein; and d) maintaining the reactor at a pressure of from about 5 Torr to about 100 Torr and the wafer at a selected elevated temperature which in combination are effective for reacting the precursor and ammonia to deposit a film on the wafer which comprises TiN, the film having increased density and reduced etch rate over films deposited by the same method but at lower than about 5 Torr pressure. Preferably and typically, the resultant film will consist essentially of TiN, with the film having in excess of 99% TiN by volume.
摘要翻译：公开了一种化学气相沉积方法，其以提高密度并降低TiN层的蚀刻速率的方式提供半导体晶片顶部的TiN保形层。该方法包括：a）将晶片定位在化学气相沉积反应器内; b）将定位的晶片加热至选定的加工温度为约200℃至约600℃; c）注入选定量的式Ti（NR 2）4的气态钛有机金属前体，其中R选自H和含碳基团; 气氨和在其内具有定位的预热晶片的反应器内的载气; 并且d）将反应器保持在约5托至约100托的压力下，并且所述晶片在选定的升高温度下，其组合对于使前体和氨反应以在包含TiN的晶片上沉积膜是有效的，该膜具有相对于通过相同方法但低于约5Torr压力沉积的膜的密度增加和蚀刻速率降低。优选并且通常，所得膜将基本上由TiN组成，膜的体积具有超过99％的TiN。

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