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1. 发明授权

US06207571B1 Self-aligned contact formation for semiconductor devices 有权
标题翻译：用于半导体器件的自对准接触形成
公开(公告)号：US06207571B1
公开(公告)日：2001-03-27
申请号：US09515804
申请日：2000-02-29
申请人： Werner Juengling , Kirk Prall , Trung T. Doan , Guy T. Blalock , David Dickerson , David S. Becker
发明人： Werner Juengling , Kirk Prall , Trung T. Doan , Guy T. Blalock , David Dickerson , David S. Becker
IPC分类号： H01L2100
CPC分类号： H01L27/10894 , H01L21/316 , H01L21/31625 , H01L21/76897
摘要： In accordance with the present invention, there is provided a method for fabricating a contact on an integrated circuit, such as a DRAM. The method includes the following steps. A gate stack is formed on the integrated circuit. A spacer is formed on sidewalls of the gate stack. An insulating film is formed on the integrated circuit. The insulating film is planarized. Finally, a gate contact opening is formed through the planarized insulating film. In one embodiment, the gate contact opening is formed by removing the insulator, spacer and insulating film by etching. In this embodiment, the insulator, spacer and insulating film are etched at substantially similar rates. As a result, the integrated circuit is tolerant of mask misalignments, and does not over-etch field oxide or create silicon nitride slivers. In another embodiment, the planarizing step is performed with chemical mechanical planarization to form a substantially flat topography on the surface of the integrated circuit. Thus, the present invention does not require lithography equipment with a relatively large field of depth. In yet a third embodiment, the method may comprise additional steps, including forming additional dielectric on the integrated circuit. Then, gate and bitline contact openings are formed through the additional dielectric. Finally, gate and bitline contacts are formed in self-alignment to the gate stacks. This embodiment may be implemented by forming the gate and bitline contact openings with an etch that removes the additional dielectric, but does not substantially remove the spacer. As a result, the bitline contact cannot be inadvertently connected to a gate stack that functions as a wordline. This connection might disable the integrated circuit.
摘要翻译：根据本发明，提供了一种用于在诸如DRAM的集成电路上制造接触的方法。该方法包括以下步骤。在集成电路上形成栅极堆叠。在栅叠层的侧壁上形成间隔物。在集成电路上形成绝缘膜。绝缘膜平坦化。最后，通过平坦化绝缘膜形成栅极接触开口。在一个实施例中，通过蚀刻去除绝缘体，间隔物和绝缘膜来形成栅极接触开口。在该实施例中，以基本相似的速率蚀刻绝缘体，间隔物和绝缘膜。因此，集成电路容忍掩模未对准，并且不会过度蚀刻场氧化物或产生氮化硅条。在另一个实施例中，平面化步骤通过化学机械平面化进行，以在集成电路的表面上形成基本平坦的形貌。因此，本发明不需要具有相当大的深度场的光刻设备。在第三个实施例中，该方法可以包括额外的步骤，包括在集成电路上形成附加电介质。然后，通过附加电介质形成栅极和位线接触开口。最后，栅极和位线触点形成为与栅极堆叠自对准。该实施例可以通过用蚀刻去除附加电介质但不基本上去除间隔物的栅极和位线接触开口来实现。因此，位线接触不能无意中连接到用作字线的栅极堆叠。此连接可能会禁用集成电路。

2. 发明授权

US6080672A Self-aligned contact formation for semiconductor devices 失效
标题翻译：用于半导体器件的自对准接触形成
公开(公告)号：US6080672A
公开(公告)日：2000-06-27
申请号：US915386
申请日：1997-08-20
申请人： Werner Juengling , Kirk Prall , Trung T. Doan , Guy T. Blalock , David Dickerson , David S. Becker
发明人： Werner Juengling , Kirk Prall , Trung T. Doan , Guy T. Blalock , David Dickerson , David S. Becker
IPC分类号： H01L21/316 , H01L21/60 , H01L21/8242 , H01L21/00
CPC分类号： H01L27/10894 , H01L21/76897 , H01L21/316 , H01L21/31625
摘要： In accordance with the present invention, there is provided a method for fabricating a contact on an integrated circuit, such as a DRAM. The method includes the following steps. A gate stack is formed on the integrated circuit. A spacer is formed on sidewalls of the gate stack. An insulating film is formed on the integrated circuit. The insulating film is planarized. Finally, a gate contact opening is formed through the planarized insulating film. In one embodiment, the gate contact opening is formed by removing the insulator, spacer and insulating film by etching. In this embodiment, the insulator, spacer and insulating film are etched at substantially similar rates. As a result, the integrated circuit is tolerant of mask misalignments, and does not over-etch field oxide or create silicon nitride slivers. In another embodiment, the planarizing step is performed with chemical mechanical planarization to form a substantially flat topography on the surface of the integrated circuit. Thus, the present invention does not require lithography equipment with a relatively large field of depth. In yet a third embodiment, the method may comprise additional steps, including forming additional dielectric on the integrated circuit. Then, gate and bitline contact openings are formed through the additional dielectric. Finally, gate and bitline contacts are formed in self-alignment to the gate stacks. This embodiment may be implemented by forming the gate and bitline contact openings with an etch that removes the additional dielectric, but does not substantially remove the spacer. As a result, the bitline contact cannot be inadvertently connected to a gate stack that functions as a wordline. This connection might disable the integrated circuit.
摘要翻译：根据本发明，提供了一种用于在诸如DRAM的集成电路上制造接触的方法。该方法包括以下步骤。在集成电路上形成栅极堆叠。在栅叠层的侧壁上形成间隔物。在集成电路上形成绝缘膜。绝缘膜平坦化。最后，通过平坦化绝缘膜形成栅极接触开口。在一个实施例中，通过蚀刻去除绝缘体，间隔物和绝缘膜来形成栅极接触开口。在该实施例中，以基本相似的速率蚀刻绝缘体，间隔物和绝缘膜。因此，集成电路容忍掩模未对准，并且不会过度蚀刻场氧化物或产生氮化硅条。在另一个实施例中，平面化步骤通过化学机械平面化进行，以在集成电路的表面上形成基本平坦的形貌。因此，本发明不需要具有相当大的深度场的光刻设备。在第三个实施例中，该方法可以包括额外的步骤，包括在集成电路上形成附加电介质。然后，通过附加电介质形成栅极和位线接触开口。最后，栅极和位线触点形成为与栅极堆叠自对准。该实施例可以通过用蚀刻去除附加电介质但不基本上去除间隔物的栅极和位线接触开口来实现。因此，位线接触不能无意中连接到用作字线的栅极堆叠。此连接可能会禁用集成电路。

3. 发明授权

US06255209B1 Methods of forming a contact having titanium formed by chemical vapor deposition 有权
标题翻译：形成通过化学气相沉积形成的具有钛的接触的方法
公开(公告)号：US06255209B1
公开(公告)日：2001-07-03
申请号：US09376023
申请日：1999-08-19
申请人： Trung T. Doan , Gurtej Singh Sandhu , Kirk Prall , Sujit Sharan
发明人： Trung T. Doan , Gurtej Singh Sandhu , Kirk Prall , Sujit Sharan
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , C23C16/02 , C23C16/0236 , C23C16/42 , H01L21/28518 , H01L21/28556 , H01L21/76855
摘要： Methods are provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). The methods include forming titanium in the contact. One method includes forming titanium by combining a titanium precursor in the presence of hydrogen, H2. Another method includes forming titanium by combining titanium tetrachloride, TiCl4, in the presence of hydrogen. A further method includes forming titanium by combining tetradimethyl amino titanium, Ti(N(CH3)2)4, in the presence of hydrogen.
摘要翻译：提供了通过化学气相沉积（CVD）在集成电路中形成接触的方法。所述方法包括在接触中形成钛。一种方法包括通过在氢气存在下将钛前体组合而形成钛。另一种方法包括在氢的存在下将四氯化钛，TiCl 4组合形成钛。另一种方法包括在氢的存在下，通过组合四（二甲基氨基）钛，Ti（N（CH 3）2）4形成钛。

4. 发明授权

US06208033B1 Apparatus having titanium silicide and titanium formed by chemical vapor deposition 有权
标题翻译：具有通过化学气相沉积形成的钛硅化物和钛的装置
公开(公告)号：US06208033B1
公开(公告)日：2001-03-27
申请号：US09377253
申请日：1999-08-19
申请人： Trung T. Doan , Gurtej Singh Sandhu , Kirk Prall , Sujit Sharan
发明人： Trung T. Doan , Gurtej Singh Sandhu , Kirk Prall , Sujit Sharan
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , C23C16/02 , C23C16/0236 , C23C16/42 , H01L21/28518 , H01L21/28556 , H01L21/76855
摘要： Apparatus having titanium silicide and titanium formed by chemical vapor deposition (CVD) in a contact. The chemical vapor deposition includes forming titanium silicide and/or titanium by combining a titanium precursor in the presence of hydrogen, H2. The chemical vapor deposition may further include forming titanium silicide and/or titanium by combining titanium tetrachloride, TiCl4, in the presence of hydrogen. The chemical vapor deposition may further include forming titanium silicide and/or by combining tetradimethyl amino titanium, Ti(N(CH3)2)4, in the presence of hydrogen. For production of titanium silicide, reaction of the titanium precursor may occur with a silicon precursor or a silicon source occurring as part of the contact. Use of a silicon precursor reduces depletion of a silicon base layer in the contact.
摘要翻译：具有通过化学气相沉积（CVD）在接触中形成的钛硅化物和钛的装置。化学气相沉积包括通过在氢气存在下将钛前体组合而形成钛硅化物和/或钛。化学气相沉积还可以包括在氢的存在下通过组合四氯化钛TiCl 4来形成硅化钛和/或钛。化学气相沉积可以进一步包括在氢的存在下形成硅化钛和/或通过组合四（二甲基氨基）钛（N（CH 3）2）4）。对于硅化钛的生产，钛前体的反应可以与作为接触部分的硅前体或硅源发生。硅前体的使用减少了接触中硅基层的耗尽。

5. 发明授权

US06472756B2 Method of forming titanium silicide and titanium by chemical vapor deposition and resulting apparatus 有权
标题翻译：通过化学气相沉积法形成钛硅化钛和钛的方法
公开(公告)号：US06472756B2
公开(公告)日：2002-10-29
申请号：US09789999
申请日：2001-02-21
申请人： Trung T. Doan , Gurtej Singh Sandhu , Kirk Prall , Sujit Sharan
发明人： Trung T. Doan , Gurtej Singh Sandhu , Kirk Prall , Sujit Sharan
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , C23C16/02 , C23C16/0236 , C23C16/42 , H01L21/28518 , H01L21/28556 , H01L21/76855
摘要： A method is provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). In one embodiment, a titanium precursor and a silicon precursor are contacted in the presence of hydrogen, to form titanium silicide. In another embodiment, a titanium precursor contacts silicon to form to form titanium silicide.
摘要翻译：提供了一种通过化学气相沉积（CVD）在集成电路中形成接触的方法。在一个实施方案中，在氢的存在下使钛前体和硅前体接触以形成硅化钛。在另一个实施方案中，钛前体与硅接触以形成硅化钛。

6. 发明授权

US06171943B2 Methods of forming a contact having titanium silicide formed by chemical vapor deposition 有权
标题翻译：通过化学气相沉积形成具有硅化钛的接触的方法
公开(公告)号：US06171943B2
公开(公告)日：2001-01-09
申请号：US09377273
申请日：1999-08-19
申请人： Trung T. Doan , Gurtej Singh Sandhu , Kirk Prall , Sujit Sharan
发明人： Trung T. Doan , Gurtej Singh Sandhu , Kirk Prall , Sujit Sharan
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , C23C16/02 , C23C16/0236 , C23C16/42 , H01L21/28518 , H01L21/28556 , H01L21/76855
摘要： A method is provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). In one embodiment, a titanium precursor and a silicon precursor are contacted in the presence of hydrogen, to form titanium silicide. In another embodiment, a titanium precursor contacts silicon to form to form titanium silicide.
摘要翻译：提供了一种通过化学气相沉积（CVD）在集成电路中形成接触的方法。在一个实施方案中，在氢的存在下使钛前体和硅前体接触以形成硅化钛。在另一个实施方案中，钛前体与硅接触以形成硅化钛。

7. 发明授权

US06255216B1 Methods of forming a contact having titanium silicide and titanium formed by chemical vapor deposition 有权
标题翻译：形成具有通过化学气相沉积形成的钛硅化物和钛的接触的方法
公开(公告)号：US06255216B1
公开(公告)日：2001-07-03
申请号：US09377265
申请日：1999-08-19
申请人： Trung T. Doan , Gurtej Singh Sandhu , Kirk Prall , Sujit Sharan
发明人： Trung T. Doan , Gurtej Singh Sandhu , Kirk Prall , Sujit Sharan
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , C23C16/02 , C23C16/0236 , C23C16/42 , H01L21/28518 , H01L21/28556 , H01L21/76855
摘要： Methods arc provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). The methods include forming titanium silicide in the contact. One method includes forming titanium silicide by combining a titanium precursor in the presence of hydrogen, H2. Another method includes forming titanium silicide by combining titanium tetrachloride, TiCl4, in the presence of hydrogen. A further method includes forming titanium silicide by combining tetradimethyl amino titanium, Ti(N(CH3)2)4, in the presence of hydrogen. The methods may further include forming titanium in the contact.
摘要翻译：提供了通过化学气相沉积（CVD）在集成电路中形成接触的方法。所述方法包括在接触中形成硅化钛。一种方法包括通过在氢气存在下将钛前体组合而形成硅化钛。另一种方法包括在氢气存在下通过组合四氯化钛TiCl 4来形成硅化钛。另一种方法包括在氢的存在下，通过组合四（二甲基氨基）钛，Ti（N（CH 3）2）4来形成硅化钛。所述方法还可以包括在接触中形成钛。

8. 发明授权

US5976976A Method of forming titanium silicide and titanium by chemical vapor deposition 失效
标题翻译：通过化学气相沉积法形成硅化钛和钛的方法
公开(公告)号：US5976976A
公开(公告)日：1999-11-02
申请号：US915986
申请日：1997-08-21
申请人： Trung T. Doan , Gurtej Singh Sandhu , Kirk Prall , Sujit Sharan
发明人： Trung T. Doan , Gurtej Singh Sandhu , Kirk Prall , Sujit Sharan
IPC分类号： C23C16/02 , C23C16/14 , C23C16/42 , H01L21/28 , H01L21/285 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76843 , C23C16/02 , C23C16/0236 , C23C16/42 , H01L21/28518 , H01L21/76855 , H01L21/28556
摘要： A method is provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). In one embodiment, a titanium precursor and a silicon precursor are contacted in the presence of hydrogen, to form titanium silicide. In another embodiment, a titanium precursor contacts silicon to form to form titanium silicide.
摘要翻译：提供了一种通过化学气相沉积（CVD）在集成电路中形成接触的方法。在一个实施方案中，在氢的存在下使钛前体和硅前体接触以形成硅化钛。在另一个实施方案中，钛前体与硅接触以形成硅化钛。

9. 发明授权

US5858865A Method of forming contact plugs 失效
标题翻译：形成接触塞的方法
公开(公告)号：US5858865A
公开(公告)日：1999-01-12
申请号：US569838
申请日：1995-12-07
申请人： Werner Juengling , Kirk Prall , Gordon Haller , David Keller , Tyler Lowrey
发明人： Werner Juengling , Kirk Prall , Gordon Haller , David Keller , Tyler Lowrey
IPC分类号： H01L21/28 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L21/3205
CPC分类号： H01L27/10888 , H01L21/28 , H01L21/768 , H01L21/76897 , H01L23/485 , H01L2924/0002 , Y10S438/978
摘要： Within an integrated circuit, a contact plug with a height not extending above the level of the gate/wordline nitride is nonetheless provided with a relatively large contact area or landing pad, significantly larger than the source/drain region to which the contact plug is electrically connected. Methods for producing the inventive contact plug include (1) use of a nitride facet etch, either (a) during a nitride spacer formation etch or (b) during a BPSG etch; (2) using at least one of (a) an isotropic photoresist etch or partial descum to narrow BPSG spacers above the gate/wordline nitride, and (b) a nitride step etch to etch the shoulder area of the gate/wordline nitride exposed by a BPSG etch; and (3) polishing a BPSG layer down to the top of a gate/wordline nitride before any doped polysilicon plug fill, masking for BPSG etch and performing a BPSG etch, etching the photoresist layer through a partial descum, and etching the shoulder area of the gate/wordline nitride exposed thereby.
摘要翻译：在集成电路中，具有不延伸在栅极/字线氮化物的高度之上的高度的接触插塞仍然设置有相对较大的接触面积或着陆焊盘，其明显大于接触插塞电接触的源极/漏极区域连接的。用于制造本发明接触塞的方法包括（1）在氮化物间隔物形成蚀刻期间使用氮化物刻面蚀刻（a）或（b）在BPSG蚀刻期间; （2）使用（a）各向同性光致抗蚀剂蚀刻或部分除去中的至少一种来窄化栅极/字线氮化物之上的BPSG间隔区，以及（b）氮化物步骤蚀刻以蚀刻暴露于栅极/字线氮化物的肩部区域 BPSG蚀刻; 并且（3）在任何掺杂的多晶硅插塞填充之前将BPSG层向下抛光到栅极/字线氮化物的顶部，掩蔽用于BPSG蚀刻和执行BPSG蚀刻，通过部分除去蚀刻光致抗蚀剂层，并蚀刻栅极/字线氮化物被曝光。

10. 发明授权

US06469389B2 Contact plug 有权
标题翻译：接触塞
公开(公告)号：US06469389B2
公开(公告)日：2002-10-22
申请号：US09567649
申请日：2000-05-09
申请人： Werner Juengling , Kirk Prall , Gordon Haller , David Keller , Tyler Lowrey
发明人： Werner Juengling , Kirk Prall , Gordon Haller , David Keller , Tyler Lowrey
IPC分类号： H01L2348
CPC分类号： H01L27/10888 , H01L21/28 , H01L21/768 , H01L21/76897 , H01L23/485 , H01L2924/0002 , Y10S438/978 , H01L2924/00
摘要： Within an integrated circuit, a contact plug with a height not extending above the level of the gate/wordline nitride is nonetheless provided with a relatively large contact area or landing pad, significantly larger than the source/drain region to which the contact plug is electrically connected. Methods for producing the inventive contact plug include (1) use of a nitride facet etch, either (a) during a nitride spacer formation etch or (b) during a BPSG etch; (2) using at least one of (a) an isotropic photoresist etch or partial descum to narrow BPSG spacers above the gate/wordline nitride, and (b) a nitride step etch to etch the shoulder area of the gate/wordline nitride exposed by a BPSG etch; and (3) polishing a BPSG layer down to the top of a gate/wordline nitride before any doped polysilicon plug fill, masking for BPSG etch and performing a BPSG etch, etching the photoresist layer through a partial descum, and etching the shoulder area of the gate/wordline nitride exposed thereby.
摘要翻译：在集成电路中，具有不延伸在栅极/字线氮化物的高度之上的高度的接触插塞仍然设置有相对较大的接触面积或着陆焊盘，其明显大于接触插塞电接触的源极/漏极区域连接的。用于制造本发明接触塞的方法包括（1）在氮化物间隔物形成蚀刻期间使用氮化物刻面蚀刻（a）或（b）在BPSG蚀刻期间; （2）使用（a）各向同性光致抗蚀剂蚀刻或部分除去中的至少一种来窄化栅极/字线氮化物之上的BPSG间隔区，以及（b）氮化物步骤蚀刻以蚀刻暴露于栅极/字线氮化物的肩部区域 BPSG蚀刻; 并且（3）在任何掺杂的多晶硅插塞填充之前将BPSG层向下抛光到栅极/字线氮化物的顶部，掩蔽用于BPSG蚀刻和执行BPSG蚀刻，通过部分除去蚀刻光致抗蚀剂层，并蚀刻栅极/字线氮化物被曝光。

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