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81. 发明授权

US07921400B1 Method for forming integrated circuit device using cell library with soft error resistant logic cells 有权
标题翻译：使用具有软电阻逻辑单元的单元库形成集成电路器件的方法
公开(公告)号：US07921400B1
公开(公告)日：2011-04-05
申请号：US12478734
申请日：2009-06-04
申请人： Chuen-Der Lien , Shih-Ked Lee
发明人： Chuen-Der Lien , Shih-Ked Lee
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/505
摘要： A cell library is disclosed that includes soft error resistant logic cells. The soft error resistant logic cells can be used along with memory cells and conventional logic cells to form integrated circuit designs having increased soft error resistance. A method for forming an integrated circuit device is disclosed in which a first integrated circuit design is formed using conventional logic cells. An iterative process is then performed in which some of the conventional logic cells are replaced with high soft error resistant logic cells to obtain a soft error resistant design. Each soft error resistant logic cell that replaces a corresponding conventional logic cell will have the same cell size as the cell that is replaced, producing a soft error resistant design that does not take up additional surface area on the semiconductor substrate.
摘要翻译：公开了包括软错误的逻辑单元的单元库。软的抗错误逻辑单元可与存储器单元和常规逻辑单元一起使用以形成具有增加的软错误电阻的集成电路设计。公开了一种用于形成集成电路器件的方法，其中使用常规逻辑单元形成第一集成电路设计。然后执行一个迭代过程，其中一些常规的逻辑单元被高的软错误抵抗的逻辑单元替换以获得软的抗错误设计。取代相应的常规逻辑单元的每个软错误抵抗逻辑单元将具有与被替换的单元相同的单元尺寸，从而产生不占用半导体衬底上的附加表面积的柔性抗错误设计。

82. 发明授权

US07582567B1 Method for forming CMOS device with self-aligned contacts and region formed using salicide process 有权
标题翻译：用于形成具有自对准触点的CMOS器件的方法和使用自对准硅化物工艺形成的区域
公开(公告)号：US07582567B1
公开(公告)日：2009-09-01
申请号：US11424333
申请日：2006-06-15
申请人： Tsengyou Syau , Shih-Ked Lee , Chuen-Der Lien
发明人： Tsengyou Syau , Shih-Ked Lee , Chuen-Der Lien
IPC分类号： H01L21/302
CPC分类号： H01L21/823814 , H01L21/823425 , H01L21/823835
摘要： A method for forming CMOS devices on a semiconductor substrate is disclosed in which gate structures are formed within both the core region and the non-core region of the semiconductor substrate. The gate structures include a gate dielectric layer and a gate film stack that includes a conductive layer and an overlying hard mask. The hard mask is then removed from the gate structures in the non-core region. A salicide process is then performed so as to form a silicide layer in the non-core region. A barrier layer is formed that extends over the core region and a pre-metal dielectric film is formed that extends over the barrier layer. A selective etch process is performed so as to form self-aligned contact openings that extend through the pre-metal dielectric film and through the barrier layer in the core region. These openings are then filled with conductive material to form self-aligned contacts in the core region. This produces a CMOS device in the core region that has high device density and includes high-speed CMOS devices the non-core region.
摘要翻译：公开了一种在半导体衬底上形成CMOS器件的方法，其中栅极结构形成在半导体衬底的芯区域和非芯区域中。栅极结构包括栅极介电层和包括导电层和上覆硬掩模的栅极膜堆叠。然后将硬掩模从非芯区域中的栅极结构移除。然后执行自对准硅化物工艺以在非芯区域中形成硅化物层。形成在芯区域上延伸的阻挡层，并且形成在阻挡层上延伸的预金属介电膜。执行选择性蚀刻工艺以形成延伸穿过预金属介电膜并通过芯区域中的阻挡层的自对准接触开口。然后用导电材料填充这些开口，以在芯区域中形成自对准的触点。这在芯区域产生具有高器件密度的CMOS器件，并且包括非核心区域的高速CMOS器件。

83. 发明授权

US07560800B1 Die seal with reduced noise coupling 有权
标题翻译：降低噪音耦合的密封
公开(公告)号：US07560800B1
公开(公告)日：2009-07-14
申请号：US11459820
申请日：2006-07-25
申请人： Chuen-Der Lien , Shih-Ked Lee
发明人： Chuen-Der Lien , Shih-Ked Lee
IPC分类号： H01L29/06
CPC分类号： H01L23/585 , H01L23/552 , H01L23/564 , H01L29/8611 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A die seal structure for sealing integrated circuit devices formed on a semiconductor substrate. The die seal structure includes a die seal and a junction diode. The die seal only connects to the semiconductor substrate through the junction diode, thereby reducing noise coupling through the die seal. In another aspect of the present invention the die seal structure includes a die seal and a bipolar structure. In this embodiment the die seal only connects to the semiconductor substrate through the bipolar structure.
摘要翻译：一种用于密封形成在半导体衬底上的集成电路器件的模封密封结构。模具密封结构包括模具密封和结二极管。管芯密封件仅通过结二极管连接到半导体衬底，从而减少通过管芯密封件的噪声耦合。在本发明的另一方面，模具密封结构包括模具密封件和双极结构。在该实施例中，管芯密封件仅通过双极结构连接到半导体衬底。

84. 发明授权

US07408751B1 Self-biased electrostatic discharge protection method and circuit 有权
标题翻译：自偏置静电放电保护方法及电路
公开(公告)号：US07408751B1
公开(公告)日：2008-08-05
申请号：US11229195
申请日：2005-09-15
申请人： Chuen-Der Lien , Shih-Ked Lee
发明人： Chuen-Der Lien , Shih-Ked Lee
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： A self-biased electrostatic discharge (ESD) protection circuit for protecting an integrated circuit operating in a normal voltage range that includes both positive and negative voltage levels is disclosed. The self-biased ESD protection circuit includes an input connection for receiving an input voltage, a protection transistor electrically coupled to the input connection, and an electrical sink. The protection transistor is operable to provide ESD protection from the input connection to the electrical sink. The self-biased ESD protection circuit also includes a metal oxide semiconductor (MOS) biasing network electrically coupled to the input connection and the protection transistor. The MOS biasing network is operable to cause the protection transistor to remain in a non-conductive state when the input voltage is in the normal operating voltage range. Upon the occurrence of an electrostatic discharge event at the input connection, the protection circuit becomes conducting to discharge ESD current from the input connection to the electrical sink.
摘要翻译：公开了一种用于保护在包括正电压和负电压电平的正常电压范围内工作的集成电路的自偏置静电放电（ESD）保护电路。自偏压ESD保护电路包括用于接收输入电压的输入连接，电耦合到输入连接的保护晶体管和电接收器。保护晶体管可操作以从输入连接到电汇的ESD保护。自偏压ESD保护电路还包括电耦合到输入连接和保护晶体管的金属氧化物半导体（MOS）偏置网络。当输入电压处于正常工作电压范围时，MOS偏置网络可操作地使保护晶体管保持在非导通状态。在输入连接处发生静电放电事件时，保护电路变为导通，以将ESD电流从输入连接放电到电汇点。

85. 发明申请

US20080122473A1 Method for improved single event latch up resistance in an integrated circuit 有权
标题翻译：在集成电路中改进单事件闭锁电阻的方法
公开(公告)号：US20080122473A1
公开(公告)日：2008-05-29
申请号：US11527374
申请日：2006-09-25
申请人： Chuen-Der Lien , Ta-Ke Tien , Pao-Lu Louis Huang
发明人： Chuen-Der Lien , Ta-Ke Tien , Pao-Lu Louis Huang
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： G01R31/2853 , G06F17/5036 , Y10S257/929
摘要： A process and system for estimating the occurrence of single event latch-up in an integrated circuit. The process involves determining the resistance between each junction and the closest appropriate tap in a regular shaped well. Each junction occurring in an irregular-shaped well is also identified. Finally, the method may make suggestions for lowering the probability that single event latch-up may occur in the integrated circuit.
摘要翻译：一种用于估计集成电路中单事件闩锁发生的过程和系统。该过程包括确定每个连接点与规则形状井中最接近的适当水龙头之间的阻力。发现在不规则形状的井中的每个连接也被识别。最后，该方法可以提出降低集成电路中可能发生单事件闩锁的可能性的建议。

86. 发明申请

US20070234125A1 Logic soft error rate prediction and improvement 有权
标题翻译：逻辑软错误率预测与改进
公开(公告)号：US20070234125A1
公开(公告)日：2007-10-04
申请号：US11395119
申请日：2006-03-31
申请人： Chuen-Der Lien , Pao-Lu Huang
发明人： Chuen-Der Lien , Pao-Lu Huang
IPC分类号： G06F11/00
CPC分类号： G01R31/31816
摘要： A process and system for estimating the soft error rate of an integrated circuit. The process involves determining the surface area of and charge stored on each logic node on the integrated circuit. Then a response curve is used to estimate the soft error rate for a logic node using the charge stored on the logic node. Different response curves exist for integrated circuits of different technologies and products. Finally, the soft error rate of the integrated circuit can be estimated using the soft error rates for each logic node.
摘要翻译：一种用于估计集成电路的软错误率的过程和系统。该过程涉及确定存储在集成电路上的每个逻辑节点上的表面积和电荷。然后使用响应曲线来使用存储在逻辑节点上的电荷来估计逻辑节点的软错误率。不同技术和产品的集成电路存在不同的响应曲线。最后，可以使用每个逻辑节点的软错误率来估计集成电路的软错误率。

87. 发明授权

US07098114B1 Method for forming cmos device with self-aligned contacts and region formed using salicide process 有权
标题翻译：用自对准接触形成cmos器件的方法和使用自对准硅化物工艺形成的区域
公开(公告)号：US07098114B1
公开(公告)日：2006-08-29
申请号：US10874980
申请日：2004-06-22
申请人： Tsengyou Syau , Shih-Ked Lee , Chuen-Der Lien
发明人： Tsengyou Syau , Shih-Ked Lee , Chuen-Der Lien
IPC分类号： H01L21/331
CPC分类号： H01L21/823814 , H01L21/823425 , H01L21/823835
摘要： A method for forming CMOS devices on a semiconductor substrate is disclosed in which gate structures are formed within both the core region and the non-core region of the semiconductor substrate. The gate structures include a gate dielectric layer and a gate film stack that includes a conductive layer and an overlying hard mask. The hard mask is then removed from the gate structures in the non-core region. A salicide process is then performed so as to form a silicide layer in the non-core region. A barrier layer is formed that extends over the core region and a pre-metal dielectric film is formed that extends over the barrier layer. A selective etch process is performed so as to form self-aligned contact openings that extend through the pre-metal dielectric film and through the barrier layer in the core region. These openings are then filled with conductive material to form self-aligned contacts in the core region. This produces a CMOS device in the core region that has high device density and includes high-speed CMOS devices the non-core region.
摘要翻译：公开了一种在半导体衬底上形成CMOS器件的方法，其中栅极结构形成在半导体衬底的芯区域和非芯区域中。栅极结构包括栅极介电层和包括导电层和上覆硬掩模的栅极膜堆叠。然后将硬掩模从非芯区域中的栅极结构移除。然后执行自对准硅化物工艺以在非芯区域中形成硅化物层。形成在芯区域上延伸的阻挡层，并且形成在阻挡层上延伸的预金属介电膜。执行选择性蚀刻工艺以形成延伸穿过预金属介电膜并通过芯区域中的阻挡层的自对准接触开口。然后用导电材料填充这些开口，以在芯区域中形成自对准的触点。这在芯区域产生具有高器件密度的CMOS器件，并且包括非核心区域的高速CMOS器件。

88. 再颁专利

USRE39227E1 Content addressable memory (CAM) arrays and cells having low power requirements 有权
标题翻译：内容可寻址存储器（CAM）阵列和具有低功率要求的单元
公开(公告)号：USRE39227E1
公开(公告)日：2006-08-08
申请号：US10403581
申请日：2003-03-31
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A content addressable memory (CAM) cell that includes a static random access memory (SRAM) cell that operates in response to a VCC supply voltage. A first set of bit lines coupled to the SRAM cell are used to transfer data values to and from the SRAM cell. The signals transmitted on the first set of bit lines have a signal swing equal to the VCC supply voltage. A second set of bit lines is coupled to receive a comparison data value. The signals transmitted on the second set of bit lines have a signal swing that is less than the VCC supply voltage. For example, the signal swing on the second set of bit lines can be as low as two transistor threshold voltages. The second set of bit lines is biased with a supply voltage that is less than the VCC supply voltage. A sensor circuit is provided for comparing the data value stored in the CAM cell with the comparison data value. The sensor circuit pre-charges a match scan line prior to a compare operation. If the data value stored in the CAM cell does not match the comparison data value, the match sense line is pulled down. The signal swing of the match sense line is smaller than the VCC supply voltage. For example, the signal swing on the match sense line can be as low as one transistor threshold voltage.
摘要翻译：一种内容可寻址存储器（CAM）单元，其包括响应于V CC电源电压工作的静态随机存取存储器（SRAM）单元。耦合到SRAM单元的第一组位线用于将数据值传送到SRAM单元和从SRAM单元传送数据值。在第一组位线上发送的信号具有等于V CC电源电压的信号摆幅。第二组位线被耦合以接收比较数据值。在第二组位线上发送的信号具有小于V CC电源电压的信号摆幅。例如，第二组位线上的信号摆幅可以低至两个晶体管阈值电压。第二组位线被供给电压偏压，该电源电压小于V CC电源电压。提供了一种传感器电路，用于将存储在CAM单元中的数据值与比较数据值进行比较。在比较操作之前，传感器电路对匹配扫描线进行预充电。如果存储在CAM单元中的数据值与比较数据值不匹配，则下拉匹配检测线。匹配检测线的信号摆幅小于V CC电源电压。例如，匹配检测线上的信号摆幅可以低至一个晶体管阈值电压。

89. 发明授权

US06560156B2 CAM circuit with radiation resistance 有权
公开(公告)号：US06560156B2
公开(公告)日：2003-05-06
申请号：US10099913
申请日：2002-03-14
申请人： Chuen-Der Lien , Michael J. Miller
发明人： Chuen-Der Lien , Michael J. Miller
IPC分类号： G11C700
CPC分类号： G11C15/046 , G11C11/4125 , G11C15/04 , G11C15/043
摘要： A CAM circuit including a RAM array, a CAM array, and a control circuit that systematically writes data from the RAM array to the CAM array, thereby preventing soft errors by continually restoring data that has been corrupted by radiation. The RAM and CAM arrays can be formed on the same substrate, but are preferably fabricated on separate substrates and mounted in a single package or on a PCB. Both the CAM and RAM can be formed using any conventional memory type (e.g., SRAM, DRAM, NVRAM), and the CAM array can be a binary, ternary, or quad CAM array. The CAM and RAM arrays can be formed on different substrates, or the same substrate. A system including an SRAM ternary CAM array and a RAM array perform quad CAM functions by performing read functions utilizing only the RAM array, while performing lookup functions using the ternary CAM array.

90. 发明授权

US06512685B1 CAM circuit with separate memory and logic operating voltages 有权
标题翻译： CAM电路具有独立的存储器和逻辑工作电压
公开(公告)号：US06512685B1
公开(公告)日：2003-01-28
申请号：US10164981
申请日：2002-06-06
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C1504
CPC分类号： G11C15/00 , G11C14/00 , G11C15/04 , G11C15/043
摘要： A CAM circuit utilizes a relatively high operating voltage to control the memory portion of each CAM cell, and a relatively low operating voltage to control the logic portion of each CAM cell. The CAM cell memory portion includes a memory (e.g., SRAM) cell controlled by a word line to store data values transmitted on complementary bit lines. The CAM cell logic portion includes a comparator that compares the stored data values with an applied data value transmitted on complementary data lines, and discharges a match line when the stored data value differs from the applied data value. The memory cell is driven using the relatively high memory operating voltage (e.g., 2.5 Volts) such that the stored charge resists soft errors. The complementary data lines and match line used to operate the comparator are driven using the relatively low logic operating voltage (e.g., 1.2 Volts) to conserve power.
摘要翻译： CAM电路利用相对较高的工作电压来控制每个CAM单元的存储器部分，以及相对低的工作电压来控制每个CAM单元的逻辑部分。 CAM单元存储器部分包括由字线控制的存储器（例如，SRAM）单元，以存储在互补位线上传输的数据值。 CAM单元逻辑部分包括比较器，用于比较存储的数据值和互补数据线上传输的应用数据值，并且当存储的数据值与应用的数据值不同时，对其进行放电。使用相对高的存储器工作电压（例如，2.5伏特）来驱动存储器单元，使得存储的电荷抵抗软错误。用于操作比较器的补充数据线和匹配线使用相对较低的逻辑工作电压（例如，1.2伏特）来驱动以节省功率。

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