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1. 发明授权

US07644311B2 Logic soft error rate prediction and improvement 有权
标题翻译：逻辑软错误率预测与改进
公开(公告)号：US07644311B2
公开(公告)日：2010-01-05
申请号：US11395119
申请日：2006-03-31
申请人： Chuen-Der Lien , Pao-Lu Louis Huang
发明人： Chuen-Der Lien , Pao-Lu Louis Huang
IPC分类号： G06F11/00
CPC分类号： G01R31/31816
摘要： A process and system for estimating the soft error rate of an integrated circuit. The process involves determining the surface area of and charge stored on each logic node on the integrated circuit. Then a response curve is used to estimate the soft error rate for a logic node using the charge stored on the logic node. Different response curves exist for integrated circuits of different technologies and products. Finally, the soft error rate of the integrated circuit can be estimated using the soft error rates for each logic node.
摘要翻译：一种用于估计集成电路的软错误率的过程和系统。该过程涉及确定存储在集成电路上的每个逻辑节点上的表面积和电荷。然后使用响应曲线来使用存储在逻辑节点上的电荷来估计逻辑节点的软错误率。不同技术和产品的集成电路存在不同的响应曲线。最后，可以使用每个逻辑节点的软错误率来估计集成电路的软错误率。

2. 发明授权

US07474011B2 Method for improved single event latch up resistance in an integrated circuit 有权
标题翻译：在集成电路中改进单事件闭锁电阻的方法
公开(公告)号：US07474011B2
公开(公告)日：2009-01-06
申请号：US11527374
申请日：2006-09-25
申请人： Chuen-Der Lien , Ta-Ke Tien , Pao-Lu Louis Huang
发明人： Chuen-Der Lien , Ta-Ke Tien , Pao-Lu Louis Huang
IPC分类号： H01L27/00 , G06F17/50
CPC分类号： G01R31/2853 , G06F17/5036 , Y10S257/929
摘要： A process and system for estimating the occurrence of single event latch-up in an integrated circuit. The process involves determining the resistance between each junction and the closest appropriate tap in a regular shaped well. Each junction occurring in an irregular-shaped well is also identified. Finally, the method may make suggestions for lowering the probability that single event latch-up may occur in the integrated circuit.
摘要翻译：一种用于估计集成电路中单事件闩锁发生的过程和系统。该过程包括确定每个连接点与规则形状井中最接近的适当水龙头之间的阻力。发现在不规则形状的井中的每个连接也被识别。最后，该方法可以提出降低集成电路中可能发生单事件闩锁的可能性的建议。

3. 发明授权

US07286438B2 Dual port memory cell with reduced coupling capacitance and small cell size 有权
标题翻译：具有减小的耦合电容和小单元尺寸的双端口存储单元
公开(公告)号：US07286438B2
公开(公告)日：2007-10-23
申请号：US11403370
申请日：2006-04-12
申请人： Chuen-Der Lien , Pao-Lu Louis Huang
发明人： Chuen-Der Lien , Pao-Lu Louis Huang
IPC分类号： G11C8/00
CPC分类号： G11C8/16 , G11C5/063 , G11C7/02 , G11C7/1075 , G11C7/18
摘要： A dual or multi port memory device including a first group of bit lines associated with the first port a second group of bit lines associated with the second port, wherein the bit lines are arranged in different metalization layers and separated horizontally to reduce one or both of stray and coupling capacitance associated with the bit lines. In one exemplary embodiment, the bit lines from each port that are in closer proximity to the bit lines of the other (or another) port are disposed in different metallization layers to reduce coupling capacitance therebetween. One or more further embodiments can include VSS or VDD line(s) located horizontally between the bit lines and metal to substrate contacts for the bit lines can be formed in opposite corners of the memory device to further reduce capacitance.
摘要翻译：一种双端口或多端口存储器件，包括与第一端口相关联的与第二端口相关联的第二组位线的第一组位线，其中位线布置在不同的金属化层中并且水平分开以减少一个或两个与位线相关的杂散和耦合电容。在一个示例性实施例中，来自更接近另一（或另一）端口的位线的每个端口的位线被布置在不同的金属化层中以减小它们之间的耦合电容。一个或多个另外的实施例可以包括水平位于位线和用于位线的金属到衬底触点之间的V SS或V DD线，可以形成为相反的存储器件的角落，以进一步降低电容。

4. 发明申请

US20080122473A1 Method for improved single event latch up resistance in an integrated circuit 有权
标题翻译：在集成电路中改进单事件闭锁电阻的方法
公开(公告)号：US20080122473A1
公开(公告)日：2008-05-29
申请号：US11527374
申请日：2006-09-25
申请人： Chuen-Der Lien , Ta-Ke Tien , Pao-Lu Louis Huang
发明人： Chuen-Der Lien , Ta-Ke Tien , Pao-Lu Louis Huang
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： G01R31/2853 , G06F17/5036 , Y10S257/929
摘要： A process and system for estimating the occurrence of single event latch-up in an integrated circuit. The process involves determining the resistance between each junction and the closest appropriate tap in a regular shaped well. Each junction occurring in an irregular-shaped well is also identified. Finally, the method may make suggestions for lowering the probability that single event latch-up may occur in the integrated circuit.
摘要翻译：一种用于估计集成电路中单事件闩锁发生的过程和系统。该过程包括确定每个连接点与规则形状井中最接近的适当水龙头之间的阻力。发现在不规则形状的井中的每个连接也被识别。最后，该方法可以提出降低集成电路中可能发生单事件闩锁的可能性的建议。

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