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81. 发明申请

US20100035419A1 PATTERN INDEPENDENT Si:C SELECTIVE EPITAXY 失效
标题翻译：图案独立Si：C选择性外观
公开(公告)号：US20100035419A1
公开(公告)日：2010-02-11
申请号：US12189344
申请日：2008-08-11
申请人： ABHISHEK DUBE , Ashima B. Chakravarti , Dominic J. Schepis
发明人： ABHISHEK DUBE , Ashima B. Chakravarti , Dominic J. Schepis
IPC分类号： H01L21/20
CPC分类号： H01L21/02381 , H01L21/02529 , H01L21/0262 , H01L21/02639 , H01L29/66636 , H01L29/7848
摘要： Trenches are formed in a silicon substrate by etching exposed portions of the silicon substrate. After covering areas on which deposition of Si:C containing material is to be prevented, selective epitaxy is performed in a single wafer chamber at a temperature from about 550° C. to about 600° C. employing a limited carrier gas flow, i.e., at a flow rate less than 12 standard liters per minute to deposit Si:C containing regions at a pattern-independent uniform deposition rate. The inventive selective epitaxy process for Si:C deposition provides a relatively high net deposition rate a high quality Si:C crystal in which the carbon atoms are incorporated into substitutional sites as verified by X-ray diffraction.
摘要翻译：通过蚀刻硅衬底的暴露部分在硅衬底中形成沟槽。在覆盖要防止沉积含Si：C的材料的区域之后，使用有限的载气流在约550℃至约600℃的温度下，在单晶片室中进行选择性外延，即，以小于12标准升/分钟的流速，以不依赖于图案的均匀沉积速率沉积含Si：C的区域。用于Si：C沉积的本发明的选择性外延工艺提供了相对较高的净沉积速率，其中通过X射线衍射验证碳原子并入到取代位置的高质量Si：C晶体。

82. 发明授权

US07622341B2 Sige channel epitaxial development for high-k PFET manufacturability 失效
标题翻译： Sige通道外延开发高k PFET可制造性
公开(公告)号：US07622341B2
公开(公告)日：2009-11-24
申请号：US12014815
申请日：2008-01-16
申请人： Michael P. Chudzik , Dominic J. Schepis , Linda Black
发明人： Michael P. Chudzik , Dominic J. Schepis , Linda Black
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/76229 , H01L21/823842 , H01L21/823878
摘要： A method for growing an epitaxial layer patterns a mask over a substrate. The mask protects first areas (N-type areas) of the substrate where N-type field effect transistors (NFETs) are to be formed and exposes second areas (P-type areas) of the substrate where P-type field effect transistors (PFETs) are to be formed. Using the mask, the method can then epitaxially grow the Silicon Germanium layer only on the P-type areas. The mask is then removed and shallow trench isolation (STI) trenches are patterned (using a different mask) in the N-type areas and in the P-type areas. This STI patterning process positions the STI trenches so as to remove edges of the epitaxial layer. The trenches are then filled with an isolation material. Finally, the NFETs are formed to have first metal gates and the PFETs are formed to have second metal gates that are different than the first metal gates. The first metal gates have a different work function than the second metal gates.
摘要翻译：用于生长外延层的方法在衬底上图案掩模。掩模保护要形成N型场效应晶体管（NFET）的衬底的第一区域（N型区域），并露出衬底的第二区域（P型区域），其中P型场效应晶体管（PFET））将被形成。使用掩模，该方法可以仅在P型区域上外延生长硅锗层。然后去除掩模，并在N型区域和P型区域中对浅沟槽隔离（STI）沟槽进行图案化（使用不同的掩模）。该STI图案化工艺定位STI沟槽以便去除外延层的边缘。然后用隔离材料填充沟槽。最后，NFET形成为具有第一金属栅极，并且PFET形成为具有与第一金属栅极不同的第二金属栅极。第一金属门具有与第二金属门不同的功函数。

83. 发明申请

US20090269926A1 POLYGRAIN ENGINEERING BY ADDING IMPURITIES IN THE GAS PHASE DURING CHEMICAL VAPOR DEPOSITION OF POLYSILICON 审中-公开
标题翻译：通过在多晶硅化学气相沉积期间在气相中添加污染物进行聚合工程
公开(公告)号：US20090269926A1
公开(公告)日：2009-10-29
申请号：US12110594
申请日：2008-04-28
申请人： Abhishek Dube , Ashima B. Chakravarti , Anthony I. Chou , Wei He , Dominic J. Schepis
发明人： Abhishek Dube , Ashima B. Chakravarti , Anthony I. Chou , Wei He , Dominic J. Schepis
IPC分类号： H01L21/44
CPC分类号： H01L21/28035 , H01L29/4925
摘要： A method of forming at least one gate conductor of a complementary metal oxide semiconductor performs a chemical vapor deposition process of polysilicon over a surface where a polysilicon gate is to be located. This deposition can be performed through a mask to form gate structures directly, or a later patterning process can pattern the polysilicon into gate structures. During the chemical vapor deposition process, the method adds impurities in the chemical vapor deposition process to optimize the grain size of the polysilicon according to a number of different methods.
摘要翻译：形成互补金属氧化物半导体的至少一个栅极导体的方法在多晶硅栅极位于的表面上进行多晶硅的化学气相沉积处理。该沉积可以通过掩模进行直接形成栅极结构，或者后来的图案化工艺可以将多晶硅图案化成栅极结构。在化学气相沉积过程中，该方法根据多种不同的方法在化学气相沉积工艺中添加杂质以优化多晶硅的晶粒尺寸。

84. 发明申请

US20090152590A1 METHOD AND STRUCTURE FOR SEMICONDUCTOR DEVICES WITH SILICON-GERMANIUM DEPOSITS 审中-公开
标题翻译：具有硅锗沉积物的半导体器件的方法和结构
公开(公告)号：US20090152590A1
公开(公告)日：2009-06-18
申请号：US11955488
申请日：2007-12-13
申请人： Thomas N. Adam , Linda Black , Huajie Chen , Dureseti Chidambarrao , Robert E. Davis , Judson R. Holt , Randolph F. Knarr , Christian Lavoie , Robert J. Purtell , Dominic J. Schepis
发明人： Thomas N. Adam , Linda Black , Huajie Chen , Dureseti Chidambarrao , Robert E. Davis , Judson R. Holt , Randolph F. Knarr , Christian Lavoie , Robert J. Purtell , Dominic J. Schepis
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66636
摘要： A method of forming a semiconductor device including forming a second deposit of silicon-germanium on a first deposit of silicon-germanium, the first deposit formed in a conduction terminal region of a substrate of the semiconductor device and having a first percentage of germanium, and the second deposit having a second percentage of germanium that is less than the first percentage and supports forming a silicide deposit on the second deposit. A structure is also provided.
摘要翻译：一种形成半导体器件的方法，包括在硅 - 锗的第一沉积物上形成硅 - 锗的第二沉积物，所述第一沉积物形成在所述半导体器件的衬底的导电末端区域中并且具有第一百分比的锗，以及所述第二沉积物具有小于所述第一百分比的第二百分比的锗，并且在所述第二沉积物上支持形成硅化物沉积物。还提供了一种结构。

85. 发明授权

US07544994B2 Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure 有权
标题翻译：具有不同通道区域高度的多个翅片的半导体结构和形成半导体结构的方法
公开(公告)号：US07544994B2
公开(公告)日：2009-06-09
申请号：US11556844
申请日：2006-11-06
申请人： Dominic J. Schepis , Huilong Zhu
发明人： Dominic J. Schepis , Huilong Zhu
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： Disclosed are embodiments of a semiconductor structure with fins that are positioned on the same planar surface of a wafer and that have channel regions with different heights. In one embodiment the different channel region heights are accomplished by varying the overall heights of the different fins. In another embodiment the different channel region heights are accomplished by varying, not the overall heights of the different fins, but rather by varying the heights of a semiconductor layer within each of the fins. The disclosed semiconductor structure embodiments allow different multi-gate non-planar FETs (i.e., tri-gate or dual-gate FETs) with different effective channel widths to be formed of the same wafer and, thus, allows the beta ratio in devices that incorporate multiple FETs (e.g., static random access memory (SRAM) cells) to be selectively adjusted.
摘要翻译：公开了具有翅片的半导体结构的实施例，翅片位于晶片的同一平面上并具有不同高度的沟道区。在一个实施例中，通过改变不同翅片的整体高度来实现不同的通道区域高度。在另一个实施例中，不同通道区域的高度是通过改变而不是不同翅片的整体高度来实现的，而是通过改变每个翅片内的半导体层的高度来实现。所公开的半导体结构实施例允许具有不同有效沟道宽度的不同的多门非平面FET（即，三栅极或双栅极FET）由相同的晶片形成，并且因此允许在包含多个FET（例如，静态随机存取存储器（SRAM）单元）被选择性地调整。

86. 发明授权

US07446350B2 Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer 有权
标题翻译：使用双埋氧化硅绝缘体上硅晶片的嵌入式硅锗
公开(公告)号：US07446350B2
公开(公告)日：2008-11-04
申请号：US10908394
申请日：2005-05-10
申请人： Huajie Chen , Dureseti Chidambarrao , Dominic J. Schepis , Henry K. Utomo
发明人： Huajie Chen , Dureseti Chidambarrao , Dominic J. Schepis , Henry K. Utomo
IPC分类号： H01L21/365
CPC分类号： H01L29/7842 , H01L27/1203 , H01L29/66628 , H01L29/66636 , H01L29/7848 , H01L29/78603 , H01L29/78618 , H01L29/78684
摘要： Disclosed is a p-type field effect transistor (pFET) structure and method of forming the pFET. The pFET comprises embedded silicon germanium in the source/drain regions to increase longitudinal stress on the p-channel and, thereby, enhance transistor performance. Increased stress is achieved by increasing the depth of the source/drain regions and, thereby, the volume of the embedded silicon germanium. The greater depth (e.g., up to 100 nm) of the stressed silicon germanium source/drain regions is achieved by using a double BOX SOI wafer. Trenches are etched through a first silicon layer and first buried oxide layer and then the stressed silicon germanium is epitaxially grown from a second silicon layer. A second buried oxide layer isolates the pFET.
摘要翻译：公开了一种形成pFET的p型场效应晶体管（pFET）结构和方法。 pFET在源极/漏极区域中包括嵌入的硅锗以增加p沟道上的纵向应力，从而增强晶体管的性能。通过增加源极/漏极区域的深度，从而增加嵌入式硅锗的体积来实现增加的应力。通过使用双BOX SOI晶片来实现应力硅锗源极/漏极区域的更大的深度（例如高达100nm）。通过第一硅层和第一掩埋氧化物层蚀刻沟槽，然后从第二硅层外延生长受应力的硅锗。第二掩埋氧化物层隔离pFET。

87. 发明申请

US20080122013A1 SEMICONDUCTOR STRUCTURE WITH MULTIPLE FINS HAVING DIFFERENT CHANNEL REGION HEIGHTS AND METHOD OF FORMING THE SEMICONDUCTOR STRUCTURE 有权
标题翻译：具有不同通道区域的多个FINS的半导体结构和形成半导体结构的方法
公开(公告)号：US20080122013A1
公开(公告)日：2008-05-29
申请号：US11556844
申请日：2006-11-06
申请人： Dominic J. Schepis , Huilong Zhu
发明人： Dominic J. Schepis , Huilong Zhu
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： Disclosed are embodiments of a semiconductor structure with fins that are positioned on the same planar surface of a wafer and that have channel regions with different heights. In one embodiment the different channel region heights are accomplished by varying the overall heights of the different fins. In another embodiment the different channel region heights are accomplished by varying, not the overall heights of the different fins, but rather by varying the heights of a semiconductor layer within each of the fins. The disclosed semiconductor structure embodiments allow different multi-gate non-planar FETs (i.e., tri-gate or dual-gate FETs) with different effective channel widths to be formed of the same wafer and, thus, allows the beta ratio in devices that incorporate multiple FETs (e.g., static random access memory (SRAM) cells) to be selectively adjusted.
摘要翻译：公开了具有翅片的半导体结构的实施例，翅片位于晶片的同一平面上并且具有不同高度的沟道区。在一个实施例中，通过改变不同翅片的整体高度来实现不同的通道区域高度。在另一个实施例中，不同通道区域的高度是通过改变而不是不同翅片的整体高度来实现的，而是通过改变每个翅片内的半导体层的高度来实现。所公开的半导体结构实施例允许具有不同有效沟道宽度的不同的多门非平面FET（即，三栅极或双栅极FET）由相同的晶片形成，并且因此允许在包含多个FET（例如，静态随机存取存储器（SRAM）单元）被选择性地调整。

88. 发明授权

US07115955B2 Semiconductor device having a strained raised source/drain 失效
标题翻译：具有应变升高源极/漏极的半导体器件
公开(公告)号：US07115955B2
公开(公告)日：2006-10-03
申请号：US10710738
申请日：2004-07-30
申请人： Brian Messenger , Renee T. Mo , Dominic J. Schepis
发明人： Brian Messenger , Renee T. Mo , Dominic J. Schepis
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66742 , H01L29/7842 , H01L29/78687
摘要： A manufacturable way to recess silicon that employs an end point detection method for the recess etch and allows tight tolerances on the recess is described for fabricating a strained raised source/drain layer. The method includes forming a monolayer comprising oxygen and carbon on a surface of a doped semiconductor substrate; forming an epi Si layer atop the doped semiconductor substrate; forming at least one gate region on the epi Si layer; selectively etching exposed portions of the epi layer, not protected by the gate region, stopping on and exposing the doped semiconductor substrate using end point detection; and forming a strained SiGe layer on the exposed doped semiconductor substrate. The strained SiGe layer serves as a raised layer in which source/drain diffusion regions can be subsequently formed.
摘要翻译：为了制造应变升高的源极/漏极层，描述了用于凹陷蚀刻采用端点检测方法以及允许在凹槽上的紧密公差的硅的可制造方法。该方法包括在掺杂的半导体衬底的表面上形成包含氧和碳的单层; 在掺杂半导体衬底的顶部形成外延Si层; 在外延Si层上形成至少一个栅极区; 选择性地蚀刻未被栅极区域保护的外延层的暴露部分，使用端点检测停止并暴露掺杂半导体衬底; 以及在所述暴露的掺杂半导体衬底上形成应变SiGe层。应变SiGe层用作可以随后形成源/漏扩散区的凸起层。

89. 发明授权

US06884667B1 Field effect transistor with stressed channel and method for making same 失效
标题翻译：具有应力通道的场效应晶体管及其制造方法
公开(公告)号：US06884667B1
公开(公告)日：2005-04-26
申请号：US10669727
申请日：2003-09-25
申请人： Bruce B. Doris , Dureseti Chidambarrao , Xavier Baie , Jack A. Mandelman , Devendra K. Sadana , Dominic J. Schepis
发明人： Bruce B. Doris , Dureseti Chidambarrao , Xavier Baie , Jack A. Mandelman , Devendra K. Sadana , Dominic J. Schepis
IPC分类号： H01L27/08 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/78 , H01L29/786 , H01L21/00
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/7842 , H01L29/78603 , H01L29/78696
摘要： Field effect transistor with increased charge carrier mobility due to stress in the current channel 22. The stress is in the direction of current flow (longitudinal). In PFET device, the stress is compressive; in NFET devices, the stress is tensile. The stress is created by a compressive film 34 in an area 32 under the channel. The compressive film pushes up on the channel 22, causing it to bend. In PFET devices, the compressive film is disposed under ends 31 of the channel (e.g. under the source and drain), thereby causing compression in an upper portion 22A of the channel. In NFET devices, the compressive film is disposed under a middle portion 40 of the channel (e.g. under the gate), thereby causing tension in the, upper portion of the channel. Therefore, both NFET and PFET device can be enhanced. A method for making the devices is included.
摘要翻译：场效应晶体管由于电流通道22中的应力而具有增加的电荷载流子迁移率。应力在电流方向（纵向）。在PFET器件中，应力是压缩的; 在NFET器件中，应力为拉伸。应力由通道下的区域32中的压缩膜34产生。压缩膜在通道22上向上推动，使其弯曲。在PFET器件中，压缩膜设置在通道的端部31（例如在源极和漏极之下），从而在通道的上部22A中引起压缩。在NFET器件中，压缩膜设置在通道的中间部分40（例如在栅极下），从而在通道的上部产生张力。因此，可以增强NFET和PFET器件。包括制造装置的方法。

90. 发明授权

US06288426B1 Thermal conductivity enhanced semiconductor structures and fabrication processes 有权
标题翻译：热导率增强的半导体结构和制造工艺
公开(公告)号：US06288426B1
公开(公告)日：2001-09-11
申请号：US09514106
申请日：2000-02-28
申请人： Robert J. Gauthier, Jr. , Dominic J. Schepis , William R. Tonti , Steven H. Voldman
发明人： Robert J. Gauthier, Jr. , Dominic J. Schepis , William R. Tonti , Steven H. Voldman
IPC分类号： H01L2900
CPC分类号： H01L29/78648 , H01L21/76264 , H01L21/76286 , H01L21/763 , H01L23/3677 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： Silicon is formed at selected locations on a substrate during fabrication of selected electronic components. A dielectric separation region is formed within the top silicon layer, and filled with a thermally conductive material. A liner material may be optionally deposited prior to depositing the thermally conductive material. In a second embodiment, a horizontal layer of thermally conductive material is also deposited in an oxide layer or bulk silicon layer below the top layer of silicon.
摘要翻译：在选择的电子部件的制造期间，在基板上的选定位置处形成硅。介电分离区形成在顶层硅层内，并填充有导热材料。衬里材料可以在沉积导热材料之前任选地沉积。在第二实施例中，水平导热材料层也沉积在硅顶层之下的氧化物层或体硅层中。

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