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1. 发明申请

US20090181507A1 SIGE CHANNEL EPITAXIAL DEVELOPMENT FOR HIGH-K PFET MANUFACTURABILITY 失效
标题翻译：用于高K PFET制造商的信号通道外延开发
公开(公告)号：US20090181507A1
公开(公告)日：2009-07-16
申请号：US12014815
申请日：2008-01-16
申请人： Michael P. Chudzik , Dominic J. Schepis , Linda Black
发明人： Michael P. Chudzik , Dominic J. Schepis , Linda Black
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/76229 , H01L21/823842 , H01L21/823878
摘要： A method for growing an epitaxial layer patterns a mask over a substrate. The mask protects first areas (N-type areas) of the substrate where N-type field effect transistors (NFETs) are to be formed and exposes second areas (P-type areas) of the substrate where P-type field effect transistors (PFETs) are to be formed. Using the mask, the method can then epitaxially grow the Silicon Germanium layer only on the P-type areas. The mask is then removed and shallow trench isolation (STI) trenches are patterned (using a different mask) in the N-type areas and in the P-type areas. This STI patterning process positions the STI trenches so as to remove edges of the epitaxial layer. The trenches are then filled with an isolation material. Finally, the NFETs are formed to have first metal gates and the PFETs are formed to have second metal gates that are different than the first metal gates. The first metal gates have a different work function than the second metal gates.
摘要翻译：用于生长外延层的方法在衬底上图案掩模。掩模保护要形成N型场效应晶体管（NFET）的衬底的第一区域（N型区域），并露出衬底的第二区域（P型区域），其中P型场效应晶体管（PFET））将被形成。使用掩模，该方法可以仅在P型区域上外延生长硅锗层。然后去除掩模，并在N型区域和P型区域中对浅沟槽隔离（STI）沟槽进行图案化（使用不同的掩模）。该STI图案化工艺定位STI沟槽以便去除外延层的边缘。然后用隔离材料填充沟槽。最后，NFET形成为具有第一金属栅极，并且PFET形成为具有与第一金属栅极不同的第二金属栅极。第一金属门具有与第二金属栅极不同的功函数。

2. 发明授权

US07622341B2 Sige channel epitaxial development for high-k PFET manufacturability 失效
标题翻译： Sige通道外延开发高k PFET可制造性
公开(公告)号：US07622341B2
公开(公告)日：2009-11-24
申请号：US12014815
申请日：2008-01-16
申请人： Michael P. Chudzik , Dominic J. Schepis , Linda Black
发明人： Michael P. Chudzik , Dominic J. Schepis , Linda Black
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/76229 , H01L21/823842 , H01L21/823878
摘要： A method for growing an epitaxial layer patterns a mask over a substrate. The mask protects first areas (N-type areas) of the substrate where N-type field effect transistors (NFETs) are to be formed and exposes second areas (P-type areas) of the substrate where P-type field effect transistors (PFETs) are to be formed. Using the mask, the method can then epitaxially grow the Silicon Germanium layer only on the P-type areas. The mask is then removed and shallow trench isolation (STI) trenches are patterned (using a different mask) in the N-type areas and in the P-type areas. This STI patterning process positions the STI trenches so as to remove edges of the epitaxial layer. The trenches are then filled with an isolation material. Finally, the NFETs are formed to have first metal gates and the PFETs are formed to have second metal gates that are different than the first metal gates. The first metal gates have a different work function than the second metal gates.
摘要翻译：用于生长外延层的方法在衬底上图案掩模。掩模保护要形成N型场效应晶体管（NFET）的衬底的第一区域（N型区域），并露出衬底的第二区域（P型区域），其中P型场效应晶体管（PFET））将被形成。使用掩模，该方法可以仅在P型区域上外延生长硅锗层。然后去除掩模，并在N型区域和P型区域中对浅沟槽隔离（STI）沟槽进行图案化（使用不同的掩模）。该STI图案化工艺定位STI沟槽以便去除外延层的边缘。然后用隔离材料填充沟槽。最后，NFET形成为具有第一金属栅极，并且PFET形成为具有与第一金属栅极不同的第二金属栅极。第一金属门具有与第二金属门不同的功函数。

3. 发明申请

US20120181631A1 METHOD AND STRUCTURE FOR PMOS DEVICES WITH HIGH K METAL GATE INTEGRATION AND SiGe CHANNEL ENGINEERING 有权
标题翻译：具有高K金属栅组合和SiGe通道工程的PMOS器件的方法和结构
公开(公告)号：US20120181631A1
公开(公告)日：2012-07-19
申请号：US13431328
申请日：2012-03-27
申请人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
发明人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
IPC分类号： H01L29/78
CPC分类号： H01L29/1054 , H01L21/0237 , H01L21/02532 , H01L21/02612 , H01L29/6659 , H01L29/66651 , H01L29/7833
摘要： Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.
摘要翻译：公开了通过使用SiGe通道来改变衬底的功函数的各种技术，其又有利于改变p型金属氧化物半导体场效应晶体管（pMOSFET）的带隙。在各种技术中，SiGe膜包括在更高掺杂的SiGe区域上方的低掺杂SiGe区域，以允许pMOSFET器件的适当阈值电压（Vt），同时防止随后的清洁和处理期间SiGe膜的点蚀，粗糙度和变薄被提供。

4. 发明授权

US08575655B2 Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering 有权
标题翻译：具有高K金属栅极集成和SiGe沟道工程的PMOS器件的方法和结构
公开(公告)号：US08575655B2
公开(公告)日：2013-11-05
申请号：US13431328
申请日：2012-03-27
申请人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
发明人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
IPC分类号： H01L29/66
CPC分类号： H01L29/1054 , H01L21/0237 , H01L21/02532 , H01L21/02612 , H01L29/6659 , H01L29/66651 , H01L29/7833
摘要： Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.
摘要翻译：公开了通过使用SiGe通道来改变衬底的功函数的各种技术，其又有利于改变p型金属氧化物半导体场效应晶体管（pMOSFET）的带隙。在各种技术中，SiGe膜包括在更高掺杂的SiGe区域上方的低掺杂SiGe区域，以允许pMOSFET器件的适当阈值电压（Vt），同时防止随后的清洁和处理期间SiGe膜的点蚀，粗糙度和变薄被提供。

5. 发明申请

US20100200937A1 METHOD AND STRUCTURE FOR PMOS DEVICES WITH HIGH K METAL GATE INTEGRATION AND SiGe CHANNEL ENGINEERING 失效
标题翻译：具有高K金属栅组合和SiGe通道工程的PMOS器件的方法和结构
公开(公告)号：US20100200937A1
公开(公告)日：2010-08-12
申请号：US12367759
申请日：2009-02-09
申请人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
发明人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
IPC分类号： H01L29/78 , H01L21/36
CPC分类号： H01L29/1054 , H01L21/0237 , H01L21/02532 , H01L21/02612 , H01L29/6659 , H01L29/66651 , H01L29/7833
摘要： Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.
摘要翻译：公开了通过使用SiGe通道来改变衬底的功函数的各种技术，其又有利于改变p型金属氧化物半导体场效应晶体管（pMOSFET）的带隙。在各种技术中，SiGe膜包括在更高掺杂的SiGe区域上方的低掺杂SiGe区域，以允许pMOSFET器件的适当阈值电压（Vt），同时防止随后的清洁和处理期间SiGe膜的点蚀，粗糙度和变薄被提供。

6. 发明授权

US08440547B2 Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering 失效
公开(公告)号：US08440547B2
公开(公告)日：2013-05-14
申请号：US12367759
申请日：2009-02-09
申请人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
发明人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L29/1054 , H01L21/0237 , H01L21/02532 , H01L21/02612 , H01L29/6659 , H01L29/66651 , H01L29/7833
摘要： Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.

7. 发明授权

US09236314B2 High-K/metal gate stack using capping layer methods, IC and related transistors 有权
标题翻译：高K /金属栅极堆叠采用封盖层法，IC及相关晶体管
公开(公告)号：US09236314B2
公开(公告)日：2016-01-12
申请号：US13433659
申请日：2012-03-29
申请人： Michael P. Chudzik , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
发明人： Michael P. Chudzik , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
IPC分类号： H01L21/8238 , H01L29/49 , H01L29/51
CPC分类号： H01L21/823857 , H01L21/823842 , H01L29/4966 , H01L29/4975 , H01L29/517
摘要： Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.
摘要翻译：公开了使用具有高k /金属栅极叠层的封盖层的IC和相关晶体管。在一个实施例中，IC包括具有包括第一金属，第二金属和第一介电层的栅电极的第一类型晶体管，第一介电层包括氧; 通过隔离区与第一型晶体管分离的第二类型晶体管，第二类型晶体管具有包括具有适合于第二类型晶体管和第一介电层的功函数的第二金属的栅电极; 并且其中所述第一类型晶体管的栅极包括在所述第一金属和所述第二金属之间的稀土金属，并且所述第二类型晶体管的栅电极包括由所述稀土金属的氧化物制成的第二电介质层。

8. 发明授权

US09093495B2 Method and structure to reduce FET threshold voltage shift due to oxygen diffusion 有权
标题翻译：减少由于氧扩散引起的FET阈值电压偏移的方法和结构
公开(公告)号：US09093495B2
公开(公告)日：2015-07-28
申请号：US13342674
申请日：2012-01-03
申请人： Christopher Vincent Baiocco , Michael P. Chudzik , Deleep R. Nair , Jay M. Shah
发明人： Christopher Vincent Baiocco , Michael P. Chudzik , Deleep R. Nair , Jay M. Shah
IPC分类号： H01L21/02 , H01L21/762 , H01L29/66 , H01L29/78
CPC分类号： H01L21/76224 , H01L21/762 , H01L29/0649 , H01L29/66537 , H01L29/783
摘要： Oxygen scavenging material embedded in an isolation structure provides improved protection of high dielectric constant (Hi-K) materials from oxygen contamination while avoiding alteration of work function and switching threshold shift in transistors including such Hi-K materials.
摘要翻译：嵌入隔离结构中的氧气清除材料提供了从氧污染中改进的高介电常数（Hi-K）材料的保护，同时避免了包括这种Hi-K材料在内的晶体管的功函数和切换阈值偏移的变化。

9. 发明申请

US20130292778A1 Techniques for the Fabrication of Thick Gate Dielectric 失效
标题翻译：厚栅电介质制造技术
公开(公告)号：US20130292778A1
公开(公告)日：2013-11-07
申请号：US13464966
申请日：2012-05-05
申请人： Eduard Albert Cartier , Michael P. Chudzik , Andreas Kerber , Siddarth Krishnan , Naim Moumen
发明人： Eduard Albert Cartier , Michael P. Chudzik , Andreas Kerber , Siddarth Krishnan , Naim Moumen
IPC分类号： H01L27/092 , H01L21/76
CPC分类号： H01L21/823857 , H01L21/76224
摘要： A method for fabricating a CMOS device includes the following steps. A wafer is provided. STI is used to form at least one active area in the wafer. A silicon oxide layer is deposited onto the wafer covering the active area. A first high-k material is deposited onto the silicon oxide layer. Portions of the silicon oxide layer and the first high-k material are selectively removed, such that the silicon oxide layer and the first high-k material remain over one or more first regions of the active area and are removed from over one or more second regions of the active area. A second high-k material is deposited onto the first high-k material over the one or more first regions of the active area and onto a surface of the wafer in the one or more second regions of the active area. A CMOS device is also provided.
摘要翻译：一种制造CMOS器件的方法包括以下步骤。提供晶片。 STI用于在晶片中形成至少一个有效区域。氧化硅层沉积在覆盖有源区的晶片上。第一高k材料沉积在氧化硅层上。选择性地去除氧化硅层和第一高k材料的部分，使得氧化硅层和第一高k材料保留在有源区的一个或多个第一区上，并从一个或多个第二个活跃区域。在有源区域的一个或多个第一区域上并且在有源区域的一个或多个第二区域中的晶片的表面上沉积第二高k材料到第一高k材料上。还提供了CMOS器件。

10. 发明授权

US08575709B2 High-k dielectric gate structures resistant to oxide growth at the dielectric/silicon substrate interface and methods of manufacture thereof 失效
标题翻译：在电介质/硅衬底界面处耐氧化物生长的高k电介质栅极结构及其制造方法
公开(公告)号：US08575709B2
公开(公告)日：2013-11-05
申请号：US13556795
申请日：2012-07-24
申请人： Huiming Bu , Michael P. Chudzik , Wei He , William K. Henson , Siddarth A. Krishnan , Unoh Kwon , Naim Moumen , Wesley C. Natzle
发明人： Huiming Bu , Michael P. Chudzik , Wei He , William K. Henson , Siddarth A. Krishnan , Unoh Kwon , Naim Moumen , Wesley C. Natzle
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L21/28088 , H01L21/2822 , H01L29/4966 , H01L29/51 , H01L29/66575
摘要： Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen.
摘要翻译：用于制造栅电极/高k电介质栅极结构的方法，其具有改善的耐电介质/硅基衬底界面处二氧化硅（氧化物）生长的能力。在一个实施例中，形成晶体管栅极结构的方法包括：将氮掺入靠近衬底表面的硅基衬底中; 在所述硅基衬底上沉积高k栅极电介质; 以及在高k电介质上沉积栅电极以形成栅极结构。在一个实施例中，栅电极包含富含钛的氮化钛以抑制氧的扩散。

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