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81. 发明授权

US07765458B1 Error pattern generation for trellis-based detection and/or decoding 有权
标题翻译：基于网格的检测和/或解码的错误模式生成
公开(公告)号：US07765458B1
公开(公告)日：2010-07-27
申请号：US11518020
申请日：2006-09-08
申请人： Shaohua Yang , Seo-How Low , Zining Wu , Gregory Burd
发明人： Shaohua Yang , Seo-How Low , Zining Wu , Gregory Burd
IPC分类号： H03M13/41
CPC分类号： H03M13/4192 , H03M13/098 , H03M13/3994 , H03M13/4138 , H03M13/4161 , H03M13/4169
摘要： The disclosed technology provides systems and methods for identifying potential error locations, patterns, and likelihood metrics in connection with trellis-based detection/decoding. In one aspect of the invention, the disclosed technology detects information that was previously encoded based on a trellis, and decodes the detected information based on the trellis to provide decoded information. The decoded information corresponds to a winning path through the trellis that ends at a winning state. The disclosed technology can identify one or more alternate paths through the trellis that also end at the winning state, and can generate a potential error pattern for each of the alternate paths.
摘要翻译：所公开的技术提供用于识别与基于网格的检测/解码相关的潜在错误位置，模式和似然度量的系统和方法。在本发明的一个方面，所公开的技术检测先前基于网格编码的信息，并且基于网格对检测到的信息进行解码以提供解码信息。解码的信息对应于通过在获胜状态结束的网格的获胜路径。所公开的技术可以识别通过网格的一个或多个备选路径，其也以胜利状态结束，并且可以为每个备选路径生成潜在的错误模式。

82. 发明授权

US07099411B1 Soft-output decoding method and apparatus for controlled intersymbol interference channels 有权
标题翻译：用于受控符号间干扰信道的软输出解码方法和装置
公开(公告)号：US07099411B1
公开(公告)日：2006-08-29
申请号：US09901507
申请日：2001-07-09
申请人： Zining Wu , Gregory Burd
发明人： Zining Wu , Gregory Burd
IPC分类号： H03D1/00
CPC分类号： H04L25/497 , H04L1/0052 , H04L1/0054 , H04L25/03286
摘要： A method of reducing complexity in a Viterbi decoding algorithm used in intersymbol interference channels is provided. The method includes the steps of identifying a survivor path for an input symbol, making a hard decision about a polarity of the input symbol based on the identified survivor path, identifying a plurality of dominant error events for which the opposite polarity would be determined for the input symbol, measuring a penalty metric value based on the identified survivor path for each of the plurality of dominant error events, choosing a dominant error event having a least penalty metric value from the identified plurality of dominant error events, and calculating an approximation to a logarithmic likelihood ratio for the input symbol based on the survivor path and the chosen dominant error event.
摘要翻译：提供了一种减少符号间干扰信道中使用的维特比解码算法的复杂度的方法。该方法包括以下步骤：识别用于输入符号的幸存路径，基于所识别的幸存路径对输入符号的极性作出硬判决，识别多个主要错误事件，为此将为输入符号，基于针对所述多个主要错误事件中的每一个的所识别的幸存路径来测量惩罚度量值，从所识别的多个主要错误事件中选择具有最小惩罚度量值的主要错误事件，以及计算近似值基于幸存者路径和选择的主要错误事件的输入符号的对数似然比。

83. 发明授权

US06965652B1 Address generator for LDPC encoder and decoder and method thereof 有权
标题翻译： LDPC编码器和解码器的地址生成器及其方法
公开(公告)号：US06965652B1
公开(公告)日：2005-11-15
申请号：US09730597
申请日：2000-12-07
申请人： Gregory Burd , Zining Wu
发明人： Gregory Burd , Zining Wu
IPC分类号： G11B20/18 , H03D1/00 , H03M13/11 , H03M13/27 , H04L1/00 , H04L27/06
CPC分类号： H04L1/0041 , G11B20/1833 , G11B2020/1836 , G11B2020/1863 , H03M13/1105 , H03M13/276 , H04L1/0045 , H04L1/0052 , H04L1/0057 , H04L1/0071
摘要： A data transmission system is provided for transmitting user data to and receiving data from a communication channel, comprising a first address generator to generate a first address in accordance with the user data. A linear block encoder encodes the user data in response to the first address from the first generator. A transmitter transmits an output of the linear block encoder to the communication channel, and a soft channel decoder to decode data. A second address generator generates a second address in accordance with the decoded data from the soft channel decoder, and a soft linear block code decoder decodes data decoded by the soft channel decoder in accordance with the second address from the second address generator.
摘要翻译：提供数据传输系统，用于将用户数据发送到通信信道并从其通信信道接收数据，包括根据用户数据生成第一地址的第一地址发生器。线性块编码器响应于来自第一发生器的第一地址对用户数据进行编码。发射机将线性块编码器的输出发送到通信信道，以及软信道解码器来解码数据。第二地址发生器根据来自软信道解码器的解码数据产生第二地址，并且软线性块码解码器根据来自第二地址发生器的第二地址对由软信道解码器解码的数据进行解码。

84. 发明授权

US08762824B2 Error pattern generation for trellis-based detection and/or decoding 有权
标题翻译：基于网格的检测和/或解码的错误模式生成
公开(公告)号：US08762824B2
公开(公告)日：2014-06-24
申请号：US12824517
申请日：2010-06-28
申请人： Shaohua Yang , Seo-How Low , Zining Wu , Gregory Burd
发明人： Shaohua Yang , Seo-How Low , Zining Wu , Gregory Burd
IPC分类号： H03M13/03 , H03M13/41 , H03M13/39
CPC分类号： H03M13/4192 , H03M13/098 , H03M13/3994 , H03M13/4138 , H03M13/4161 , H03M13/4169
摘要： The disclosed technology provides systems and methods for identifying potential error locations, patterns, and likelihood metrics in connection with trellis-based detection/decoding. In one aspect of the invention, the disclosed technology detects information that was previously encoded based on a trellis, and decodes the detected information based on the trellis to provide decoded information. The decoded information corresponds to a winning path through the trellis that ends at a winning state. The disclosed technology can identify one or more alternate paths through the trellis that also end at the winning state, and can generate a potential error pattern for each of the alternate paths.
摘要翻译：所公开的技术提供用于识别与基于网格的检测/解码相关的潜在错误位置，模式和似然度量的系统和方法。在本发明的一个方面，所公开的技术检测先前基于网格编码的信息，并且基于网格对检测到的信息进行解码以提供解码信息。解码的信息对应于通过在获胜状态结束的网格的获胜路径。所公开的技术可以识别通过网格的一个或多个备选路径，其也以胜利状态结束，并且可以为每个备选路径生成潜在的错误模式。

85. 发明授权

US08543886B1 Parity insertion for inner architecture 失效
标题翻译：内部架构的奇偶校验插入
公开(公告)号：US08543886B1
公开(公告)日：2013-09-24
申请号：US13422364
申请日：2012-03-16
申请人： Zining Wu , Panu Chaichanavong , Gregory Burd
发明人： Zining Wu , Panu Chaichanavong , Gregory Burd
IPC分类号： H03M13/00
CPC分类号： H03M13/2945 , G11B20/1426 , G11B20/1833 , G11B2020/1222 , G11B2020/1836 , G11B2020/185 , G11B2020/1853 , G11B2020/1856 , G11B2220/2516 , G11B2220/2562 , H03M5/145 , H03M13/2906 , H03M13/31
摘要： A coding system for digital data. The coding system includes a constrained encoder module configured to generate encoded data based on a first constrained code; a bit insertion module configured to insert at least one bit location in the encoded data; and an inner encoding module configured to (i) generate inner-code parity bits based on the encoded data, and (ii) program the inner-code parity bits into the at least one bit location.
摘要翻译：数字数据编码系统。编码系统包括被配置为基于第一约束码产生编码数据的约束编码器模块; 配置成在编码数据中插入至少一个位位置的位插入模块; 以及内部编码模块，其被配置为（i）基于所述编码数据生成内部码奇偶校验位，以及（ii）将所述内部码奇偶校验位编程到所述至少一个比特位置中。

86. 发明授权

US08484537B1 Systems and methods for data-path protection 有权
标题翻译：数据路径保护的系统和方法
公开(公告)号：US08484537B1
公开(公告)日：2013-07-09
申请号：US12950779
申请日：2010-11-19
申请人： Tang Heng , Gregory Burd , Soichi Isono , Son Hong Ho , Vincent Wong , Zining Wu
发明人： Tang Heng , Gregory Burd , Soichi Isono , Son Hong Ho , Vincent Wong , Zining Wu
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： G11B20/1803 , H03M13/09 , H03M13/253 , H03M13/2915
摘要： A system including a first buffer module, a first encoder module, a control module, and a second buffer module. The first buffer module receives (i) a first block and (ii) a first logical block address (LBA) for the first block from a host, where the first block includes first data. The first encoder module generates a first checksum based on (i) the first data and (ii) the first LBA. The control module generates a second block, where the second block includes (i) the first data, (ii) the first LBA, and (iii) the first checksum. The second buffer module receives a third block from the first buffer module, where the third block includes a second LBA. The second buffer module determines whether the third block is different than the first block depending on whether the second LBA in the third block is different than the first LBA in the second block.
摘要翻译：一种包括第一缓冲器模块，第一编码器模块，控制模块和第二缓冲器模块的系统。第一缓冲器模块从主机接收（i）第一块和（ii）第一块的第一逻辑块地址（LBA），其中第一块包括第一数据。第一编码器模块基于（i）第一数据和（ii）第一LBA产生第一校验和。控制模块生成第二块，其中第二块包括（i）第一数据，（ii）第一LBA，和（iii）第一校验和。第二缓冲器模块从第一缓冲器模块接收第三块，其中第三块包括第二LBA。第二缓冲器模块根据第三块中的第二LBA是否不同于第二块中的第一LBA来确定第三块是否不同于第一块。

87. 发明授权

US08484531B1 Post-processing decoder of LDPC codes for improved error floors 有权
标题翻译： LDPC码的后处理解码器，用于改进错误层
公开(公告)号：US08484531B1
公开(公告)日：2013-07-09
申请号：US13494747
申请日：2012-06-12
申请人： Nedeljko Varnica , Gregory Burd , Zining Wu
发明人： Nedeljko Varnica , Gregory Burd , Zining Wu
IPC分类号： G06F11/00
CPC分类号： H03M13/1111 , H03M13/1142
摘要： Systems and methods are provided for decoding received codewords using an LDPC code. An LDPC post-processor is disclosed for performing post-processing when standard LDPC decoding fails due to a trapping set. The LDPC post-processor may direct the LDPC decoder to decode the received codeword again, but may change some of the inputs to the LDPC decoder so that the LDPC decoder does not fail in the same way. In one embodiment, the LDPC post-processor may modify the symbol positions in the received codeword that correspond to a particular unsatisfied check. In another embodiment, the LDPC post-processor may modify the messages in the decoder's iterative message algorithm that correspond to the symbol positions.
摘要翻译：提供了使用LDPC码对接收到的码字进行解码的系统和方法。公开了一种用于在标准LDPC解码由于陷阱集合而失败时执行后处理的LDPC后处理器。 LDPC后处理器可以引导LDPC解码器再次对接收的码字进行解码，但是可以将LDPC解码器的一些输入改变为使得LDPC解码器不以相同的方式失效。在一个实施例中，LDPC后处理器可以修改对应于特定不满足检查的接收码字中的符号位置。在另一个实施例中，LDPC后处理器可以修改对应于符号位置的解码器的迭代消息算法中的消息。

88. 发明授权

US08312354B1 Method and apparatus for improved performance of iterative decoders on channels with memory 有权
标题翻译：用于改善具有存储器的通道上的迭代解码器性能的方法和装置
公开(公告)号：US08312354B1
公开(公告)日：2012-11-13
申请号：US12336280
申请日：2008-12-16
申请人： Nedeljko Varnica , Nitin Nangare , Gregory Burd , Zining Wu
发明人： Nedeljko Varnica , Nitin Nangare , Gregory Burd , Zining Wu
IPC分类号： H03M13/45
CPC分类号： H03M13/6331 , H03M13/1105 , H03M13/2957 , H03M13/3905 , H03M13/4138
摘要： Systems and methods for improving the performance of iterative decoders on various channels with memory are disclosed. These systems and methods may reduce the frequency or number of situations in which the iterative decoder cannot produce decoded data that matches the data that was originally sent in a communications or data storage system. The iterative decoder includes a SISO channel detector and an ECC decoder and decodes the coded information according to at least one iterative decoding algorithm in regular decoding mode and/or at least one iterative decoding algorithm in error-recovery mode.
摘要翻译：公开了用于改善具有存储器的各种通道上的迭代解码器的性能的系统和方法。这些系统和方法可以减少迭代解码器不能产生与最初在通信或数据存储系统中发送的数据匹配的解码数据的情况的频率或数量。迭代解码器包括SISO信道检测器和ECC解码器，并且按照常规解码模式中的至少一个迭代解码算法和/或错误恢复模式中的至少一个迭代解码算法解码编码信息。

89. 发明授权

US08291290B1 Methods and algorithms for joint channel-code decoding of linear block codes 有权
标题翻译：线性块码联合通道码解码的方法和算法
公开(公告)号：US08291290B1
公开(公告)日：2012-10-16
申请号：US12498320
申请日：2009-07-06
申请人： Gregory Burd , Zining Wu
发明人： Gregory Burd , Zining Wu
IPC分类号： H03M13/09 , H03M13/29
CPC分类号： G11B20/1833 , G11B2020/1836 , G11B2020/1843 , G11B2020/1853 , G11B2020/1859 , G11B2020/1863 , G11B2220/2516
摘要： Circuits, architectures, methods and algorithms for joint channel-code decoding of linear block codes, and more particularly, for identifying and correcting one or more errors in a code word and/or for encoding CRC (or parity) information. In one aspect, the invention focuses on use of (i) remainders, syndromes or other polynomials and (ii) Gaussian elimination to determine and correct errors. Although this approach may be suboptimal, the present error checking and/or detection scheme involves simpler computations and/or manipulations than conventional schemes, and is generally easier to implement logically. Since the complexity of parity-based error correction schemes increases disproportionately to the number of potential error events, the present invention meets a long-felt need for a scheme to manage error detection and/or correction in systems (such as magnetic recording applications) where there may be a relatively large number of likely error events, thereby advantageously improving reliability and/or performance in channel communications.
摘要翻译：更具体地说，用于识别和校正码字中的一个或多个错误和/或用于对CRC（或奇偶校验）信息进行编码的电路，架构，方法和算法。一方面，本发明着重于（i）余数，综合征或其他多项式的使用，以及（ii）高斯消除来确定和纠正错误。尽管该方法可能不是最佳的，但是当前的错误检查和/或检测方案涉及比常规方案更简单的计算和/或操作，并且通常更容易在逻辑上实现。由于基于奇偶校验的纠错方案的复杂性与潜在错误事件的数量不成比例地增加，本发明满足了对在系统（例如磁记录应用）中管理错误检测和/或校正的方案的长期需求，其中可能存在相对大量的可能的错误事件，从而有利地提高了信道通信中的可靠性和/或性能。

90. 发明授权

US08230312B1 Iterative decoder memory arrangement 有权
标题翻译：迭代解码器存储器布置
公开(公告)号：US08230312B1
公开(公告)日：2012-07-24
申请号：US12350885
申请日：2009-01-08
申请人： Engling Yeo , Panu Chaichanavong , Nedeljko Varnica , Gregory Burd , Zining Wu
发明人： Engling Yeo , Panu Chaichanavong , Nedeljko Varnica , Gregory Burd , Zining Wu
IPC分类号： H03M13/03
CPC分类号： H03M13/1117 , H03M13/114 , H03M13/116 , H03M13/2957 , H03M13/4138 , H03M13/6325 , H03M13/6343 , H03M13/6561
摘要： The present disclosure includes apparatus, systems and techniques relating to iterative decoder memory arrangement. In some implementations, an apparatus includes a memory module to communicate with an iterative code decoder. The memory module includes a single R memory component to store R data associated with a current codeword, and R data associated with a previous codeword. The memory module includes a Q memory component to store Q data associated with the current codeword, and Q data associated with the previous codeword. The memory module includes a channel detector memory component to store channel extrinsic information.
摘要翻译：本公开包括与迭代解码器存储器布置相关的装置，系统和技术。在一些实现中，装置包括与迭代码解码器通信的存储器模块。存储器模块包括用于存储与当前码字相关联的R数据的单个R存储器组件和与先前码字相关联的R数据。存储器模块包括用于存储与当前码字相关联的Q数据的Q存储器组件和与先前码字相关联的Q数据。存储器模块包括用于存储信道外在信息的信道检测器存储器组件。

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