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1. 发明授权

US08522123B1 Iterative decoder memory arrangement 有权
标题翻译：迭代解码器存储器布置
公开(公告)号：US08522123B1
公开(公告)日：2013-08-27
申请号：US13556063
申请日：2012-07-23
申请人： Engling Yeo , Panu Chaichanavong , Nedeljko Varnica , Gregory Burd , Zining Wu
发明人： Engling Yeo , Panu Chaichanavong , Nedeljko Varnica , Gregory Burd , Zining Wu
IPC分类号： H03M13/03
CPC分类号： H03M13/1117 , H03M13/114 , H03M13/116 , H03M13/2957 , H03M13/4138 , H03M13/6325 , H03M13/6343 , H03M13/6561
摘要： The present disclosure includes apparatus, systems and techniques relating to iterative decoder memory arrangement. A described apparatus includes a single R memory component including R banks, a Q memory component including Q banks, a channel detector memory component to store channel extrinsic information associated with current and previous codewords, and an iterative decoder communicatively coupled with the single R memory component, the Q memory component, and the channel detector memory component. The apparatus can be configured to alternate among the R banks for storing R data associated with a current codeword. The apparatus can be configured to alternate among the Q banks for storing Q data associated with a current codeword.
摘要翻译：本公开包括与迭代解码器存储器布置相关的装置，系统和技术。所描述的装置包括包括R组的单个R存储器组件，包括Q组的Q存储器组件，用于存储与当前和先前码字相关联的频道外在信息的信道检测器存储器组件，以及与单个R存储器组件通信耦合的迭代解码器，Q存储器组件和通道检测器存储器组件。该装置可以被配置为在R组之间交替存储用于存储与当前码字相关联的R数据。该装置可以被配置为在Q组之间交替存储用于存储与当前码字相关联的Q数据。

2. 发明授权

US08230312B1 Iterative decoder memory arrangement 有权
标题翻译：迭代解码器存储器布置
公开(公告)号：US08230312B1
公开(公告)日：2012-07-24
申请号：US12350885
申请日：2009-01-08
申请人： Engling Yeo , Panu Chaichanavong , Nedeljko Varnica , Gregory Burd , Zining Wu
发明人： Engling Yeo , Panu Chaichanavong , Nedeljko Varnica , Gregory Burd , Zining Wu
IPC分类号： H03M13/03
CPC分类号： H03M13/1117 , H03M13/114 , H03M13/116 , H03M13/2957 , H03M13/4138 , H03M13/6325 , H03M13/6343 , H03M13/6561
摘要： The present disclosure includes apparatus, systems and techniques relating to iterative decoder memory arrangement. In some implementations, an apparatus includes a memory module to communicate with an iterative code decoder. The memory module includes a single R memory component to store R data associated with a current codeword, and R data associated with a previous codeword. The memory module includes a Q memory component to store Q data associated with the current codeword, and Q data associated with the previous codeword. The memory module includes a channel detector memory component to store channel extrinsic information.
摘要翻译：本公开包括与迭代解码器存储器布置相关的装置，系统和技术。在一些实现中，装置包括与迭代码解码器通信的存储器模块。存储器模块包括用于存储与当前码字相关联的R数据的单个R存储器组件和与先前码字相关联的R数据。存储器模块包括用于存储与当前码字相关联的Q数据的Q存储器组件和与先前码字相关联的Q数据。存储器模块包括用于存储信道外在信息的信道检测器存储器组件。

3. 发明授权

US08307268B2 Iterative decoder systems and methods 有权
标题翻译：迭代解码器系统和方法
公开(公告)号：US08307268B2
公开(公告)日：2012-11-06
申请号：US12329581
申请日：2008-12-06
申请人： Panu Chaichanavong , Nedeljko Varnica , Nitin Nangare , Gregory Burd , Zining Wu
发明人： Panu Chaichanavong , Nedeljko Varnica , Nitin Nangare , Gregory Burd , Zining Wu
IPC分类号： G06F11/00
CPC分类号： H03M13/41 , G11B20/1426 , G11B20/1803 , G11B2020/10759 , G11B2020/1457 , H03M13/09 , H03M13/1105 , H03M13/1111 , H03M13/1114 , H03M13/13 , H03M13/29 , H03M13/2948 , H03M13/3746 , H03M13/4146 , H03M13/6343 , H03M13/6502 , H03M13/6561
摘要： Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. This may allow for a 1/(1+D) precoder that may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.
摘要翻译：提供了系统和方法，用于改进迭代解码器系统的设计和性能。在一些实施例中，迭代解码器可以通过FIR RAM从FIR样本去耦，从而导致较不复杂的设计和较短的处理时间。在一些实施例中，当在迭代解码器的SOVA和LDPC之间传递信息时，可以使用中间存储器。在一些实施例中，可以在每次LDPC迭代期间从从LDPC接收的信息中连续序列化所需的SOVA信息。在一些实施例中，HR RLL编码器的1 /（1 + D2）预编码器可以被分成两个串行1 /（1 + D）个预编码器。一个1 /（1 + D）预编码器可以被拉出HR RLL编码器外部并与迭代解码器结合使用。这可以允许可以与迭代解码器一起使用的1 /（1 + D）预编码器，同时保持由HR RLL编码器对编码信息施加的RLL约束。

4. 发明申请

US20090150746A1 ITERATIVE DECODER SYSTEMS AND METHODS 有权
标题翻译：迭代解码器系统和方法
公开(公告)号：US20090150746A1
公开(公告)日：2009-06-11
申请号：US12329581
申请日：2008-12-06
申请人： Panu Chaichanavong , Nedeljko Varnica , Nitin Nangare , Gregory Burd , Zining Wu
发明人： Panu Chaichanavong , Nedeljko Varnica , Nitin Nangare , Gregory Burd , Zining Wu
IPC分类号： H03M13/05 , G06F11/07
CPC分类号： H03M13/41 , G11B20/1426 , G11B20/1803 , G11B2020/10759 , G11B2020/1457 , H03M13/09 , H03M13/1105 , H03M13/1111 , H03M13/1114 , H03M13/13 , H03M13/29 , H03M13/2948 , H03M13/3746 , H03M13/4146 , H03M13/6343 , H03M13/6502 , H03M13/6561
摘要： Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. This may allow for a 1/(1+D) precoder that may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.
摘要翻译：提供了系统和方法，用于改进迭代解码器系统的设计和性能。在一些实施例中，迭代解码器可以通过FIR RAM从FIR样本去耦，从而导致较不复杂的设计和较短的处理时间。在一些实施例中，当在迭代解码器的SOVA和LDPC之间传递信息时，可以使用中间存储器。在一些实施例中，可以在每次LDPC迭代期间从从LDPC接收的信息中连续序列化所需的SOVA信息。在一些实施例中，HR RLL编码器的1 /（1 + D2）预编码器可以被分成两个串行，1 /（1 + D）个预编码器。一个1 /（1 + D）预编码器可以被拉出HR RLL编码器外部并与迭代解码器结合使用。这可以允许可以与迭代解码器一起使用的1 /（1 + D）预编码器，同时保持由HR RLL编码器对编码信息施加的RLL约束。

5. 发明授权

US08739009B1 Methods and apparatus for defect detection and correction via iterative decoding algorithms 有权
标题翻译：用于通过迭代解码算法进行缺陷检测和校正的方法和装置
公开(公告)号：US08739009B1
公开(公告)日：2014-05-27
申请号：US12328561
申请日：2008-12-04
申请人： Nedeljko Varnica , Yifei Zhang , Panu Chaichanavong , Gregory Burd
发明人： Nedeljko Varnica , Yifei Zhang , Panu Chaichanavong , Gregory Burd
IPC分类号： G06F11/00
CPC分类号： G06F11/0763 , G11B20/1833 , G11B2020/185 , H03M13/1111 , H03M13/2957 , H03M13/373 , H03M13/4138 , H03M13/6325 , H03M13/6343
摘要： In iterative decoding, a data recovery scheme corrects for corrupted or defective data by determining reliability metrics for blocks of decoded data. Block or windowed detectors generate block reliability metrics for data blocks (rather than individual bits) of decoded data using soft information from the regular decoding mode or from new iterative decoding iterations performed during error recovery mode. An error recovery system triggers corrective decoding of selected data blocks based on the block reliability metrics, by for example, comparing the block reliability metrics to a threshold or by selecting an adjustable number of the least reliable data blocks.
摘要翻译：在迭代解码中，数据恢复方案通过确定解码数据块的可靠性度量来校正损坏或缺陷数据。块或窗口检测器使用来自常规解码模式的软信息或在错误恢复模式期间执行的新的迭代解码迭代来生成解码数据的数据块（而不是单独位）的块可靠性度量。错误恢复系统通过例如将块可靠性度量与阈值进行比较或者通过选择可调节数量的最不可靠的数据块来触发基于块可靠性度量来对所选数据块的校正解码。

6. 发明授权

US08683274B1 Error correction coding for varying signal-to-noise ratio channels 有权
标题翻译：改变信噪比通道的纠错编码
公开(公告)号：US08683274B1
公开(公告)日：2014-03-25
申请号：US13179429
申请日：2011-07-08
申请人： Nedeljko Varnica , Gregory Burd , Zining Wu
发明人： Nedeljko Varnica , Gregory Burd , Zining Wu
IPC分类号： G06F11/00
CPC分类号： H03M13/1148 , H03M13/033 , H03M13/1102 , H03M13/353
摘要： An ERSEC system that applies a level of error correction that is inversely related to susceptibility to error as indicated by a signal-to-noise ratio (SNR) profile of a channel. The SNR profile is estimated, detected or retrieved from an external source. The ERSEC system is used with any channel for which the SNRs can vary spatially, temporally or both.
摘要翻译： ERSEC系统，其应用与通道的信噪比（SNR）轮廓所指示的与误差易感性成反比关系的纠错水平。从外部源估计，检测或检索SNR分布。 ERSEC系统与任何可以在空间上，时间上或两者上变化的信道一起使用。

7. 发明授权

US08489977B2 Low-density parity check codes for holographic storage 有权
标题翻译：用于全息存储的低密度奇偶校验码
公开(公告)号：US08489977B2
公开(公告)日：2013-07-16
申请号：US13475848
申请日：2012-05-18
申请人： Nedeljko Varnica , Seo-How Low , Gregory Burd , Zining Wu
发明人： Nedeljko Varnica , Seo-How Low , Gregory Burd , Zining Wu
IPC分类号： G06F11/10 , G06F11/30
CPC分类号： H03M13/116 , G11B20/1833 , G11B2020/185 , G11B2220/2504 , G11B2220/2508 , H03M13/036 , H03M13/6516
摘要： Systems and methods for constructing low-density parity check codes for holographic storage are provided. The methods include selecting parameters of a low-density parity check code, determining the number of bit processing elements and the amount of memory in an accompanying decoder, and constructing a mother matrix representation of a quasi-cyclic parity check matrix. The low-density parity check codes are optimized for performance, memory considerations, and throughput.
摘要翻译：提供了构建用于全息存储的低密度奇偶校验码的系统和方法。所述方法包括选择低密度奇偶校验码的参数，确定伴随的解码器中的比特处理元素的数量和存储量，以及构造准循环奇偶校验矩阵的母矩阵表示。针对性能，内存考虑和吞吐量优化了低密度奇偶校验码。

8. 发明授权

US08219878B1 Post-processing decoder of LDPC codes for improved error floors 有权
标题翻译： LDPC码的后处理解码器，用于改进错误层
公开(公告)号：US08219878B1
公开(公告)日：2012-07-10
申请号：US12327627
申请日：2008-12-03
申请人： Nedeljko Varnica , Gregory Burd , Zining Wu
发明人： Nedeljko Varnica , Gregory Burd , Zining Wu
IPC分类号： G06F11/00
CPC分类号： H03M13/1111 , H03M13/1142
摘要： Systems and methods are provided for decoding received codewords using an LDPC code. An LDPC post-processor is disclosed for performing post-processing when standard LDPC decoding fails due to a trapping set. The LDPC post-processor may direct the LDPC decoder to decode the received codeword again, but may change some of the inputs to the LDPC decoder so that the LDPC decoder does not fail in the same way. In one embodiment, the LDPC post-processor may modify the symbol positions in the received codeword that correspond to a particular unsatisfied check. In another embodiment, the LDPC post-processor may modify the messages in the decoder's iterative message algorithm that correspond to the symbol positions.
摘要翻译：提供了使用LDPC码对接收到的码字进行解码的系统和方法。公开了一种用于在标准LDPC解码由于陷阱集合而失败时执行后处理的LDPC后处理器。 LDPC后处理器可以引导LDPC解码器再次对接收的码字进行解码，但是可以将LDPC解码器的一些输入改变为使得LDPC解码器不以相同的方式失效。在一个实施例中，LDPC后处理器可以修改对应于特定不满足检查的接收码字中的符号位置。在另一个实施例中，LDPC后处理器可以修改对应于符号位置的解码器的迭代消息算法中的消息。

9. 发明授权

US08316287B1 Low-density parity check codes for holographic storage 有权
标题翻译：用于全息存储的低密度奇偶校验码
公开(公告)号：US08316287B1
公开(公告)日：2012-11-20
申请号：US11893936
申请日：2007-08-17
申请人： Nedeljko Varnica , Seo-How Low , Gregory Burd , Zining Wu
发明人： Nedeljko Varnica , Seo-How Low , Gregory Burd , Zining Wu
IPC分类号： G06F11/08 , G06F11/27
CPC分类号： H03M13/116 , G11B20/1833 , G11B2020/185 , G11B2220/2504 , G11B2220/2508 , H03M13/036 , H03M13/6516
摘要： Systems and methods for constructing low-density parity check codes for holographic storage are provided. The methods include selecting parameters of a low-density parity check code, determining the number of bit processing elements and the amount of memory in an accompanying decoder, and constructing a mother matrix representation of a quasi-cyclic parity check matrix. The low-density parity check codes are optimized for performance, memory considerations, and throughput.
摘要翻译：提供了构建用于全息存储的低密度奇偶校验码的系统和方法。所述方法包括选择低密度奇偶校验码的参数，确定伴随的解码器中的比特处理元素的数量和存储量，以及构造准循环奇偶校验矩阵的母矩阵表示。针对性能，内存考虑和吞吐量优化了低密度奇偶校验码。

10. 发明授权

US08312341B1 Interleaved error correction coding for channels with non-uniform SNRs 有权
标题翻译：具有不均匀SNR的信道的交织纠错编码
公开(公告)号：US08312341B1
公开(公告)日：2012-11-13
申请号：US11951062
申请日：2007-12-05
申请人： Nedeljko Varnica , Gregory Burd , Zining Wu
发明人： Nedeljko Varnica , Gregory Burd , Zining Wu
IPC分类号： G06F11/00 , G06F11/30 , G08C25/00 , H03M13/00 , H04L1/00
CPC分类号： H03M13/353 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/27 , H03M13/29 , H03M13/2957 , H03M13/356 , H04L1/0001 , H04L1/0057 , H04L1/0071
摘要： Generation of code words for error correction coding (ECC) of a channel with a non-uniform signal-to-noise ratio (SNR) is provided. A channel SNR profile is accessed, which can also include determining the channel profile. The channel profile characterizes sections of the channel having like SNR values. Each section of the channel is partitioned into a number of partitions. The number of partitions of each section equals a number of code words for the channel. The code words are generated by interleaving the partitions from each section such that an average SNR of each code word is made substantially the same as an average SNR of the channel.
摘要翻译：提供了具有不均匀信噪比（SNR）的信道的纠错编码（ECC）的码字的生成。访问信道SNR简档，其还可以包括确定信道简档。信道简档表征具有类似SNR值的信道的部分。通道的每个部分被分割成多个分区。每个部分的分区数等于通道的代码字数。通过交织来自每个部分的分区来产生码字，使得每个码字的平均SNR基本上与信道的平均SNR基本相同。

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