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1. 发明授权

US08484537B1 Systems and methods for data-path protection 有权
标题翻译：数据路径保护的系统和方法
公开(公告)号：US08484537B1
公开(公告)日：2013-07-09
申请号：US12950779
申请日：2010-11-19
申请人： Tang Heng , Gregory Burd , Soichi Isono , Son Hong Ho , Vincent Wong , Zining Wu
发明人： Tang Heng , Gregory Burd , Soichi Isono , Son Hong Ho , Vincent Wong , Zining Wu
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： G11B20/1803 , H03M13/09 , H03M13/253 , H03M13/2915
摘要： A system including a first buffer module, a first encoder module, a control module, and a second buffer module. The first buffer module receives (i) a first block and (ii) a first logical block address (LBA) for the first block from a host, where the first block includes first data. The first encoder module generates a first checksum based on (i) the first data and (ii) the first LBA. The control module generates a second block, where the second block includes (i) the first data, (ii) the first LBA, and (iii) the first checksum. The second buffer module receives a third block from the first buffer module, where the third block includes a second LBA. The second buffer module determines whether the third block is different than the first block depending on whether the second LBA in the third block is different than the first LBA in the second block.
摘要翻译：一种包括第一缓冲器模块，第一编码器模块，控制模块和第二缓冲器模块的系统。第一缓冲器模块从主机接收（i）第一块和（ii）第一块的第一逻辑块地址（LBA），其中第一块包括第一数据。第一编码器模块基于（i）第一数据和（ii）第一LBA产生第一校验和。控制模块生成第二块，其中第二块包括（i）第一数据，（ii）第一LBA，和（iii）第一校验和。第二缓冲器模块从第一缓冲器模块接收第三块，其中第三块包括第二LBA。第二缓冲器模块根据第三块中的第二LBA是否不同于第二块中的第一LBA来确定第三块是否不同于第一块。

2. 发明授权

US08373422B2 Integrated systems testing 有权
标题翻译：集成系统测试
公开(公告)号：US08373422B2
公开(公告)日：2013-02-12
申请号：US13006958
申请日：2011-01-14
申请人： Saeed Azimi , Son Hong Ho
发明人： Saeed Azimi , Son Hong Ho
IPC分类号： G01R31/04 , G01R31/3187
CPC分类号： G11B20/182 , G01R31/3004 , G01R31/31716 , G01R31/31717 , G11B5/455
摘要： A system including an interface and a plurality of solder joint testing modules. The interface is configured to receive test configuration data to configure each of a plurality of integrated system test (IST) modules. Each of the plurality of solder joint testing modules is configured to, based on the test configuration data, i) apply a pulse having a predetermined amplitude and width to a solder joint associated with a respective one of the plurality of IST modules, ii) monitor a resultant waveform that is generated in response to the pulse, and iii) determine an integrity of the solder joint in response to the resultant waveform. Each of the plurality of solder joint testing modules and the respective ones of the plurality of IST modules are located on a same system on chip (SOC).
摘要翻译：一种包括接口和多个焊点测试模块的系统。该接口被配置为接收测试配置数据以配置多个集成系统测试（IST）模块中的每一个。多个焊点测试模块中的每一个被配置为：基于测试配置数据，i）将具有预定幅度和宽度的脉冲施加到与多个IST模块中的相应一个模块相关联的焊点，ii）监视响应于脉冲而产生的合成波形，以及iii）响应于所得到的波形来确定焊点的完整性。多个焊点测试模块中的每一个和多个IST模块中的相应的IST模块位于相同的片上系统（SOC）上。

3. 发明申请

US20110283035A1 Hybrid Storage System With Control Module Embedded Solid-State Memory 有权
标题翻译：具有控制模块嵌入式固态存储器的混合存储系统
公开(公告)号：US20110283035A1
公开(公告)日：2011-11-17
申请号：US13098719
申请日：2011-05-02
申请人： Sehat Sutardja , Son Hong Ho
发明人： Sehat Sutardja , Son Hong Ho
IPC分类号： G06F13/14
CPC分类号： G06F3/0685 , G06F3/0619 , G06F3/0626 , G06F3/0655 , G06F3/0658 , G06F3/0679 , G06F3/068
摘要： A hybrid control module includes a host interface control module configured to transfer data to and from a host interface. A first embedded multi-media card (eMMC) interface is configured to (i) connect to a second eMMC interface of a control module embedded solid-state memory (SSM) and (ii) transfer the data between the hybrid control module and the control module embedded SSM. A buffer management module is (i) in communication with the host interface control module, the first eMMC interface and a disk access control module and (ii) configured to buffer the data in volatile memory. The data is received by the buffer management module and from at least one of the host interface control module, the first eMMC interface, or the disk access control module.
摘要翻译：混合控制模块包括主机接口控制模块，其被配置为向主机接口传送数据和从主机接口传送数据。第一嵌入式多媒体卡（eMMC）接口被配置为（i）连接到嵌入式固态存储器（SSM）的控制模块的第二eMMC接口，和（ii）在混合控制模块和控制器之间传送数据模块嵌入式SSM。缓冲器管理模块是（i）与主机接口控制模块，第一eMMC接口和磁盘访问控制模块通信，以及（ii）配置为缓存易失性存储器中的数据。数据由缓冲器管理模块和主机接口控制模块，第一eMMC接口或磁盘访问控制模块中的至少一个接收。

4. 发明申请

US20110112788A1 Integrated Systems Testing 有权
标题翻译：综合系统测试
公开(公告)号：US20110112788A1
公开(公告)日：2011-05-12
申请号：US13006958
申请日：2011-01-14
申请人： Saeed Azimi , Son Hong Ho
发明人： Saeed Azimi , Son Hong Ho
IPC分类号： G06F19/00
CPC分类号： G11B20/182 , G01R31/3004 , G01R31/31716 , G01R31/31717 , G11B5/455
摘要： A hard disk drive system comprises an interface that receives test configuration data, that transmits test result data, and that transmits and receives application data. A system on chip (SOC) includes integrated system test (IST) modules. A memory module communicates with the SOC and includes memory and an IST module. One of the IST modules communicates with the interface and is a master IST module that receives the test configuration data and that configures others of the IST modules for testing a component of the hard disk drive system.
摘要翻译：硬盘驱动器系统包括接收测试配置数据，发送测试结果数据以及发送和接收应用数据的接口。片上系统（SOC）包括集成系统测试（IST）模块。存储器模块与SOC通信并且包括存储器和IST模块。其中一个IST模块与接口进行通信，是一个主IST模块，可接收测试配置数据，并配置其他IST模块，以测试硬盘驱动器系统的组件。

5. 发明授权

US06249896B1 Error-tolerant sync detection for DVD optical disks using programmable sequence of sync marks 有权
标题翻译：使用可编程序同步标记的DVD光盘进行容错同步检测
公开(公告)号：US06249896B1
公开(公告)日：2001-06-19
申请号：US09251724
申请日：1999-02-17
申请人： Son Hong Ho , Hung Cao Nguyen , Phuc Thanh Tran
发明人： Son Hong Ho , Hung Cao Nguyen , Phuc Thanh Tran
IPC分类号： G11B2700
CPC分类号： G11B20/1813 , G11B27/3027 , G11B2220/2562
摘要： Synchronization (sync) marks on a digital-versatile disk (DVD) optical disk are initially detected and later used to adjust bit timing after jitter has occurred. Each DVD physical sector contains many sync marks in a predefined sequence. Each sync mark has a sync-code field that varies for the sync marks in a sector, and a fixed sync pattern that is constant for all sync marks. The first sync mark is detected at initialization by detecting a previous sequence of sync codes of sync marks that precede the first sync mark. The sequence is programmable so that one to seven sync marks are in the sequence searched for. Detection for sync marks with bit errors can still occur since a programmable number of bit errors are allowed in each sync code and in the fixed sync pattern. One of the sync codes can be missed in the sequence and detection still made, allowing tolerance of errors in the sync marks when longer sequences of sync codes are matched. Once initial sync is made, the bit timing is adjusted when too many pseudo-sync clocks are inserted for sync marks missed due to jitter. An early and a late window around the expected sync point are used to enable re-sync to a detected fixed sync pattern.
摘要翻译：最初检测到数字通用光盘（DVD）光盘上的同步（同步）标记，稍后用于调整抖动发生后的位时序。每个DVD物理扇区以预定义的顺序包含许多同步标记。每个同步标记具有对于扇区中的同步标记而变化的同步码字段，以及对于所有同步标记是恒定的固定同步模式。通过检测在第一同步标记之前的同步标记的同步码的先前序列，在初始化时检测第一同步标记。该序列是可编程的，以便搜索到一个到七个同步标记。由于可以在每个同步码和固定同步码型中允许可编程位数的错误，所以仍然会发生具有位错误的同步标记的检测。其中一个同步代码可能会被错过，并且仍然进行检测，从而允许在较长序列的同步码匹配时容许同步标记中的错误。一旦进行初始同步，当针对由于抖动丢失的同步标记插入太多伪同步时钟时，调整位定时。围绕预期同步点的早期和晚期窗口用于使得能够重新同步到检测到的固定同步模式。

6. 发明申请

US20120182640A1 DUAL CHANNEL HDD SYSTEMS AND METHODS 有权
标题翻译：双通道HDD系统和方法
公开(公告)号：US20120182640A1
公开(公告)日：2012-07-19
申请号：US13352744
申请日：2012-01-18
申请人： Son Hong Ho
发明人： Son Hong Ho
IPC分类号： G11B5/09 , G11B27/36
CPC分类号： G11B5/09 , G11B5/59666 , G11B19/044 , G11B20/10527 , G11B20/1883 , G11B2020/1062 , G11B2220/2516
摘要： A hard disk drive system includes a first channel module and a second channel module. The first channel module is configured to receive a first data from or transfer the first data to a first amplifier module of a hard disk assembly when reading from or writing to a first surface of a disk of the hard disk assembly. The second channel module is configured to receive a second data from or transfer the second data to a second amplifier module of the hard disk assembly when reading or writing to a second surface of the disk while the first channel module receives the first data from or transfers the first data to the first amplifier module.
摘要翻译：硬盘驱动器系统包括第一通道模块和第二通道模块。第一通道模块被配置为当从硬盘组件的盘的第一表面读取或写入硬盘组件的第一表面时从第一数据接收第一数据或将其传送到硬盘组件的第一放大器模块。第二通道模块被配置为当第一通道模块从第一通道模块或第二通道模块接收到第一数据时，在读取或写入盘的第二表面时从第二数据接收第二数据或将其传送到硬盘组件的第二放大器模块将第一个数据传送到第一个放大器模块。

7. 发明授权

US07840878B1 Systems and methods for data-path protection 有权
标题翻译：数据路径保护的系统和方法
公开(公告)号：US07840878B1
公开(公告)日：2010-11-23
申请号：US11711286
申请日：2007-02-27
申请人： Heng Tang , Gregory Burd , Soichi Isono , Son Hong Ho , Vincent Wong , Zining Wu
发明人： Heng Tang , Gregory Burd , Soichi Isono , Son Hong Ho , Vincent Wong , Zining Wu
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： G11B20/1803 , H03M13/09 , H03M13/253 , H03M13/2915
摘要： A system includes a host first-in first-out (FIFO) module, a first encoder module, a control module, a disk FIFO module, and a second encoder module. The host FIFO module receives a block having data and selectively receives a host logical block address (HLBA). The first encoder module generates a first checksum based on the data and the HLBA and generates a first encoded block. The control module appends the HLBA to the first encoded block and generates an appended block. The disk FIFO module receives the block from the host FIFO module. The second encoder module selectively generates a second checksum based on the HLBA and the data in the block received by the disk FIFO module. The second encoder module compares the block received by the disk FIFO module to the block received by the host FIFO module based on the first and second checksums.
摘要翻译：系统包括主机先进先出（FIFO）模块，第一编码器模块，控制模块，盘FIFO模块和第二编码器模块。主机FIFO模块接收具有数据的块并选择性地接收主机逻辑块地址（HLBA）。第一编码器模块基于数据和HLBA生成第一校验和，并生成第一编码块。控制模块将HLBA附加到第一编码块并生成附加块。磁盘FIFO模块从主机FIFO模块接收该块。第二编码器模块基于HLBA和由盘FIFO模块接收的块中的数据选择性地产生第二校验和。第二编码器模块基于第一和第二校验和将由盘FIFO模块接收的块与由主机FIFO模块接收的块进行比较。

8. 发明授权

US6105107A ATAPI state machine controlled by a microcontroller for interfacing a DVD controller with an ATA host bus 失效
标题翻译：由微控制器控制的ATAPI状态机用于将DVD控制器与ATA主机总线进行接口
公开(公告)号：US6105107A
公开(公告)日：2000-08-15
申请号：US126118
申请日：1998-07-30
申请人： Son Hong Ho , Kevin Hung Tonthat
发明人： Son Hong Ho , Kevin Hung Tonthat
IPC分类号： G06F3/06 , G06F11/10 , G06F12/00
CPC分类号： G06F3/0607 , G06F11/10 , G06F3/0632 , G06F3/0677
摘要： A digital-versatile disk (DVD) controller interfaces to an AT bus using ATAPI commands delivered in command packets. A microcontroller executes firmware routines to control the servo that positions the read head, and reads data sectors from the DVD disk. The microcontroller also performs error correction on the DVD data in a disk buffer. A host state machine is used to interface to the AT bus. State transitions in the host state machine are enabled or blocked by the microcontroller by setting auto-transition bits in a state-control register. The microcontroller can set auto bits to allow the host state machine to automatically receive multi-byte command packets, or to transfer data or send status to the host without microcontroller intervention. The microcontroller also has the option of performing any of these steps manually, such as for more complex ATAPI commands. Overlapping ATAPI commands are allowed when the AT bus is released. The host state machine can be programmed to wait for a service command from the host after the bus is released, and then automatically transfer data or status. Transfer errors send interrupts to the microcontroller so it can execute recovery routines.
摘要翻译：数字通用磁盘（DVD）控制器使用ATAPI命令与命令包中的ATAPI命令相连接。微控制器执行固件程序来控制定位读取头的伺服器，并从DVD盘读取数据扇区。微控制器还对磁盘缓冲区中的DVD数据执行纠错。主机状态机用于与AT总线的接口。通过在状态控制寄存器中设置自动转换位，微控制器启用或阻止主机状态机中的状态转换。微控制器可以设置自动位以允许主机状态机自动接收多字节命令数据包，或者在无需微控制器干预的情况下传输数据或发送状态到主机。微控制器还可以手动执行这些步骤，例如更复杂的ATAPI命令。当AT总线被释放时，允许重叠的ATAPI命令。总线释放后，主机状态机可编程为等待来自主机的服务命令，然后自动传输数据或状态。传输错误向微控制器发送中断，因此可以执行恢复例程。

9. 发明授权

US08782336B2 Hybrid storage system with control module embedded solid-state memory 有权
标题翻译：具有控制模块嵌入式固态存储器的混合存储系统
公开(公告)号：US08782336B2
公开(公告)日：2014-07-15
申请号：US13098719
申请日：2011-05-02
申请人： Sehat Sutardja , Son Hong Ho
发明人： Sehat Sutardja , Son Hong Ho
IPC分类号： G06F7/64
CPC分类号： G06F3/0685 , G06F3/0619 , G06F3/0626 , G06F3/0655 , G06F3/0658 , G06F3/0679 , G06F3/068
摘要： A hybrid control module includes a host interface control module configured to transfer data to and from a host interface. A first embedded multi-media card (eMMC) interface is configured to (i) connect to a second eMMC interface of a control module embedded solid-state memory (SSM) and (ii) transfer the data between the hybrid control module and the control module embedded SSM. A buffer management module is (i) in communication with the host interface control module, the first eMMC interface and a disk access control module and (ii) configured to buffer the data in volatile memory. The data is received by the buffer management module and from at least one of the host interface control module, the first eMMC interface, or the disk access control module.
摘要翻译：混合控制模块包括主机接口控制模块，其被配置为向主机接口传送数据和从主机接口传送数据。第一嵌入式多媒体卡（eMMC）接口被配置为（i）连接到嵌入式固态存储器（SSM）的控制模块的第二eMMC接口，和（ii）在混合控制模块和控制器之间传送数据模块嵌入式SSM。缓冲器管理模块是（i）与主机接口控制模块，第一eMMC接口和磁盘访问控制模块通信，以及（ii）配置为缓存易失性存储器中的数据。数据由缓冲器管理模块和主机接口控制模块，第一eMMC接口或磁盘访问控制模块中的至少一个接收。

10. 发明授权

US08570681B2 Dual channel HDD systems and methods 有权
标题翻译：双通道HDD系统和方法
公开(公告)号：US08570681B2
公开(公告)日：2013-10-29
申请号：US13352744
申请日：2012-01-18
申请人： Son Hong Ho
发明人： Son Hong Ho
IPC分类号： G11B5/02
CPC分类号： G11B5/09 , G11B5/59666 , G11B19/044 , G11B20/10527 , G11B20/1883 , G11B2020/1062 , G11B2220/2516
摘要： A hard disk drive system includes a first channel module and a second channel module. The first channel module is configured to receive a first data from or transfer the first data to a first amplifier module of a hard disk assembly when reading from or writing to a first surface of a disk of the hard disk assembly. The second channel module is configured to receive a second data from or transfer the second data to a second amplifier module of the hard disk assembly when reading or writing to a second surface of the disk while the first channel module receives the first data from or transfers the first data to the first amplifier module.
摘要翻译：硬盘驱动器系统包括第一通道模块和第二通道模块。第一通道模块被配置为当从硬盘组件的盘的第一表面读取或写入硬盘组件的第一表面时，从第一数据接收第一数据或将第一数据传送到硬盘组件的第一放大器模块。第二通道模块被配置为当第一通道模块从第一通道模块或第二通道模块接收到第一数据时，在读取或写入盘的第二表面时从第二数据接收第二数据或将其传送到硬盘组件的第二放大器模块将第一个数据传送到第一个放大器模块。

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