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81. 发明授权

US07194704B2 Design layout preparing method 有权
标题翻译：设计布局准备方法
公开(公告)号：US07194704B2
公开(公告)日：2007-03-20
申请号：US11012491
申请日：2004-12-16
申请人： Toshiya Kotani , Shigeki Nojima , Suigen Kyoh , Kyoko Izuha , Ryuji Ogawa , Satoshi Tanaka , Soichi Inoue , Hirotaka Ichikawa
发明人： Toshiya Kotani , Shigeki Nojima , Suigen Kyoh , Kyoko Izuha , Ryuji Ogawa , Satoshi Tanaka , Soichi Inoue , Hirotaka Ichikawa
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G06F17/5081 , H01L21/0271
摘要： There is disclosed a method of producing a design layout by optimizing at least one of design rule, process proximity correction parameter and process parameter, including calculating a processed pattern shape based on a design layout and a process parameter, extracting a dangerous spot having an evaluation value with respect to the processed pattern shape, which does not satisfy a predetermined tolerance, generating a repair guideline of the design layout based on a pattern included in the dangerous spot, and repairing that portion of the design layout which corresponds to the dangerous spot based on the repair guideline.
摘要翻译：公开了一种通过优化设计规则，过程接近校正参数和过程参数中的至少一个来生成设计布局的方法，包括基于设计布局和过程参数来计算处理的图案形状，提取具有评估的危险点相对于不满足预定公差的加工图案形状的值，基于包含在危险点中的图案生成设计布局的修理指南，并且修复与危险点对应的设计布局的那部分在维修准则上。

82. 发明授权

US07181707B2 Method of setting process parameter and method of setting process parameter and/or design rule 有权
标题翻译：设置过程参数的方法和设置过程参数和/或设计规则的方法
公开(公告)号：US07181707B2
公开(公告)日：2007-02-20
申请号：US10385628
申请日：2003-03-12
申请人： Toshiya Kotani , Satoshi Tanaka , Koji Hashimoto , Soichi Inoue , Ichiro Mori
发明人： Toshiya Kotani , Satoshi Tanaka , Koji Hashimoto , Soichi Inoue , Ichiro Mori
IPC分类号： G06F17/50 , G06K9/00
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a third pattern by using the process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer in an etching process, obtaining an evaluation value by comparing the third pattern with the first pattern, determining whether the evaluation value satisfies a preset condition, and changing the process parameter information when the evaluation value is found not to satisfy the preset condition.
摘要翻译：公开了一种设置用于制造半导体集成电路的工艺参数的方法，包括通过使用工艺参数信息来校正第一图案以获得第二图案，第一图案是对应于半导体集成电路的设计布局的图案，通过使用处理参数信息来预测第三图案，在蚀刻工艺中，第三图案是对应于第二图案并且将形成在半导体晶片上的图案，通过将第三图案与第一图案进行比较来获得评估值判定评估值是否满足预设条件，以及当评估值不满足预设条件时，改变处理参数信息。

83. 发明授权

US06964031B2 Mask pattern generating method and manufacturing method of semiconductor apparatus 失效
标题翻译：半导体装置的掩模图案生成方法和制造方法
公开(公告)号：US06964031B2
公开(公告)日：2005-11-08
申请号：US10255832
申请日：2002-09-27
申请人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue , Sachiko Kobayashi , Hirotaka Ichiakwa
发明人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue , Sachiko Kobayashi , Hirotaka Ichiakwa
IPC分类号： H01L21/027 , G03F1/00 , G03F1/36 , G06F17/50 , H01L21/00
CPC分类号： G03F1/36
摘要： A mask pattern generation method of generating a mask pattern from a designed pattern, comprising preparing the designed pattern, preparing a correction parameter, preparing a first correction library in which a plurality of pairs of an edge coordinate group and a correction value group to correct the edge coordinate group is registered, acquiring edge coordinate groups of the designed patterns, generating a second correction library in which only the plurality of pairs of an edge coordinate group agreeing with the acquired edge coordinate group and the correction value group is registered in the first correction library and simulation using the correction parameter, and correcting the designed pattern using the second correction library.
摘要翻译：一种从设计图案生成掩模图案的掩模图案生成方法，包括准备设计图案，准备校正参数，准备第一校正库，其中多对边缘坐标组和校正值组校正第登记边缘坐标组，获取所设计图案的边缘坐标组，生成第二校正库，其中在所述第一校正中仅登记与获取的边缘坐标组和校正值组一致的边缘坐标组的多对对库和模拟，并使用第二校正库校正设计的模式。

84. 发明授权

US06901577B2 Pattern forming method and semiconductor device manufactured by using said pattern forming method 有权
公开(公告)号：US06901577B2
公开(公告)日：2005-05-31
申请号：US10183572
申请日：2002-06-28
申请人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
IPC分类号： G03F1/00 , G03F1/36 , G03F1/68 , G03F1/70 , G03F7/20 , H01L21/027 , H01L21/302 , H01L21/3065 , G06F17/50 , G06F9/45
CPC分类号： G03F1/36 , Y10S438/926
摘要： A pattern forming method includes determining an allowable value of an etching conversion difference, obtaining a maximum distance between patterns generating the etching conversion difference within the allowable value, the patterns including main patterns or both main patterns and a dummy pattern, preparing a first design layout in which a first distance between the main patterns is smaller than the maximum distance, or a second design layout in which a second distance between the main patterns and the dummy pattern is smaller than the maximum distance, performing a design data conversion based on the first or second design layout to form first or second design data, and forming the main patterns by using the first design data, or forming both the main patterns and the dummy pattern by using the second design data.

85. 发明申请

US20050089768A1 Method of creating predictive model, method of managing process steps, method of manufacturing semiconductor device, method of manufacturing photo mask, and computer program product 有权
标题翻译：创建预测模型的方法，管理工艺步骤的方法，制造半导体器件的方法，制造光罩的方法以及计算机程序产品
公开(公告)号：US20050089768A1
公开(公告)日：2005-04-28
申请号：US10927218
申请日：2004-08-27
申请人： Satoshi Tanaka , Soichi Inoue , Koji Hashimoto , Shigeru Hasebe
发明人： Satoshi Tanaka , Soichi Inoue , Koji Hashimoto , Shigeru Hasebe
IPC分类号： G03F1/36 , G03F1/68 , G06F17/50 , H01L21/02 , H01L21/027 , G03C5/00 , G03F9/00
CPC分类号： G03F1/36 , G06F17/5068
摘要： A method of creating a predictive model of a process proximity effect comprises: preparing a predictive model of a process proximity effect including a non-determined parameter; and determining the non-determined parameter, the method comprises: preparing a pattern group for modeling, the pattern group comprising a plurality of repetition patterns, the plurality of repetition patterns being obtained by changing a first and second dimensions of a repetition pattern which repeats a basic pattern, the first dimension defining the basic pattern, and the second dimension defining repetition of the basic pattern; selecting a predetermined repetition pattern from the pattern group for modeling, the basic pattern of the predetermined repetition pattern corresponding to a pattern which is to be formed on a wafer and has a predetermined dimension; and determining the non-determined parameter in the predictive model based on the predetermined repetition pattern and the pattern having the predetermined dimension.
摘要翻译：一种创建过程接近效应的预测模型的方法包括：准备包括非确定参数的过程接近效应的预测模型; 并且确定所述未确定的参数，所述方法包括：准备用于建模的图案组，所述图案组包括多个重复图案，所述多个重复图案是通过改变重复图案的重复图案的第一和第二维度而获得的基本图案，定义基本图案的第一维度和定义基本图案重复的第二维度; 从所述图案组中选择预定的重复图案以进行建模，所述预定重复图案的基本图案与将要形成在晶片上并且具有预定尺寸的图案相对应; 以及基于预定重复图案和具有预定尺寸的图案来确定预测模型中的未确定参数。

86. 发明申请

US20050030502A1 Photomask, exposure control method and method of manufacturing a semiconductor device 审中-公开
标题翻译：光掩模，曝光控制方法和制造半导体器件的方法
公开(公告)号：US20050030502A1
公开(公告)日：2005-02-10
申请号：US10874192
申请日：2004-06-24
申请人： Tadahito Fujisawa , Soichi Inoue , Satoshi Tanaka , Masafumi Asano
发明人： Tadahito Fujisawa , Soichi Inoue , Satoshi Tanaka , Masafumi Asano
IPC分类号： G03B27/42 , G03F1/26 , G03F1/38 , G03F1/44 , G03F1/68 , G03F1/70 , G03F7/20 , H01L21/027 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522
CPC分类号： G03F1/44
摘要： A photomask transferring a light shield film pattern formed on a transparent substrate by a projection exposure apparatus, comprising a circuit pattern for transferring a predetermined pattern to a resist film, and an exposure monitor mark, the exposure monitor mark being formed in a manner that blocks having a predetermined width p, which are not resolved by the projection exposure apparatus, are intermittently or continuously arrayed along one direction, light shield and transmission portions are arrayed along one direction in each of the blocks, the blocks are arrayed so that a dimension ratio of the light shield and transmission portions of the blocks simply changes and the phase difference of exposure light passing through adjacent light transmission portions is approximately 180°.
摘要翻译：一种光掩模，其通过投影曝光装置将形成在透明基板上的遮光膜图案转印，所述投影曝光装置包括用于将预定图案转印到抗蚀剂膜的电路图案，以及曝光监视标记，所述曝光监视标记以块具有未被投影曝光装置解析的预定宽度p沿着一个方向间歇地或连续地排列，在每个块中沿着一个方向排列有光屏蔽和透射部分，块被排列成使得尺寸比的光屏蔽和透射部分简单地改变，并且穿过相邻光传输部分的曝光光的相位差大约为180°。

87. 发明授权

US06340542B1 Method of manufacturing a semiconductor device, method of manufacturing a photomask, and a master mask 失效
标题翻译：制造半导体器件的方法，制造光掩模的方法和母掩模
公开(公告)号：US06340542B1
公开(公告)日：2002-01-22
申请号：US09455320
申请日：1999-12-06
申请人： Soichi Inoue , Suigen Kyoh , Iwao Higashikawa , Ichiro Mori
发明人： Soichi Inoue , Suigen Kyoh , Iwao Higashikawa , Ichiro Mori
IPC分类号： G03F900
CPC分类号： G03F7/70433 , G03F1/36
摘要： A method of manufacturing a semiconductor device, light is applied through the cell patterns made in master masks, thereby transferring the cell patterns to, and forming the cell patterns on, a wafer. On the basis of layout data representing a layout diagram of the semiconductor device, the pattern data of the device is divided along the boundaries of the function blocks of the device, generating pattern data items. Master masks are prepared in accordance with the pattern data items. Light is applied to the wafer, first through the master mask and then through the master mask. The cell patterns made in the master masks are transferred to the wafer.
摘要翻译：一种制造半导体器件的方法，通过在主掩模中制成的电池图案来施加光，从而将晶片图案转移到晶片上并形成晶胞图案。基于表示半导体器件的布局图的布局数据，沿着器件的功能块的边界划分器件的图案数据，生成图案数据项。根据模式数据项准备主掩模。将光施加到晶片上，首先通过主掩模，然后通过主掩模。在主掩模中制成的电池图案被转移到晶片。

88. 发明授权

US06335145B1 Pattern forming method and pattern forming apparatus 失效
标题翻译：图案形成方法和图案形成装置
公开(公告)号：US06335145B1
公开(公告)日：2002-01-01
申请号：US09705870
申请日：2000-11-06
申请人： Soichi Inoue , Iwao Higashikawa , Yoji Ogawa , Shigehiro Hara , Kazuko Yamamoto
发明人： Soichi Inoue , Iwao Higashikawa , Yoji Ogawa , Shigehiro Hara , Kazuko Yamamoto
IPC分类号： G03C500
CPC分类号： G03F7/70425
摘要： A method of forming a pattern for a semiconductor device comprises the steps of forming a photosensitive film on a substrate and radiating the photosensitive film on the substrate with a beam of a predetermined shape consisting of one of a charged particle beam and an electromagnetic beam, thereby forming an exposed region of a desired shape, the latter step including the step of exposing each of unit regions by a single shot of the beam of the predetermined shape for a predetermined period of time, repeating the exposure a plurality of times, and butt-joining the exposed unit regions to thereby form the exposed region of the desired shape, wherein, in the step of forming the exposed region of the desired shape, butting portions of the unit regions are situated in a first area of a layer to be formed other than a second area in the layer in which predetermined characteristics of a function of the semiconductor device are determined by a pattern width of the exposed region in association with another pattern formed in another layer.
摘要翻译：一种形成半导体器件的图案的方法包括以下步骤：在基片上形成感光膜，并用由带电粒子束和电磁束之一构成的预定形状的光束将光敏膜照射在基片上，由此形成期望形状的曝光区域，后一步骤包括通过预定时间段的光束的单次曝光曝光每个单元区域的步骤，重复曝光多次，接合曝光的单元区域，从而形成所需形状的曝光区域，其中在形成所需形状的曝光区域的步骤中，单元区域的对接部分位于待形成的层的第一区域中比在半导体器件的功能的预定特性由相关联中的暴露区域的图案宽度确定的层中的第二区域 n在另一层中形成另一图案。

89. 发明授权

US6165652A Pattern forming method and pattern forming apparatus 失效
标题翻译：图案形成方法和图案形成装置
公开(公告)号：US6165652A
公开(公告)日：2000-12-26
申请号：US461332
申请日：1999-12-15
申请人： Soichi Inoue , Iwao Higashikawa , Yoji Ogawa , Shigehiro Hara , Kazuko Yamamoto
发明人： Soichi Inoue , Iwao Higashikawa , Yoji Ogawa , Shigehiro Hara , Kazuko Yamamoto
IPC分类号： H01L21/027 , G03F7/20 , G03F9/00
CPC分类号： G03F7/70425
摘要： A method of forming a photomask of a semiconductor device comprising the steps of forming a photosensitive film on a substrate and exposing the photosensitive film on the substrate by radiating with a radiation beam a plurality of butting unit regions defining butting portions between the butting unit regions and controlling said radiating of the butting unit region so that the butting portions of the butting unit regions are formed only in portions corresponding to isolation regions or alternatively, they are not formed in portions corresponding to contact areas.
摘要翻译：一种形成半导体器件的光掩模的方法，包括以下步骤：在衬底上形成感光膜，并通过用辐射束辐射将感光膜暴露在衬底上，多个对接单元区域限定对接单元区域和对接单元区域之间的对接部分控制对接单元区域的辐射，使得对接单元区域的对接部分仅形成在对应于隔离区域的部分中，或者替代地，它们不形成在对应于接触区域的部分中。

90. 发明授权

US06110647A Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06110647A
公开(公告)日：2000-08-29
申请号：US024225
申请日：1998-02-17
申请人： Soichi Inoue , Hisashi Kaneko , Masahiko Hasunuma , Takamasa Usui , Masami Aoki , Kazuko Yamamoto , Sachiko Kobayashi
发明人： Soichi Inoue , Hisashi Kaneko , Masahiko Hasunuma , Takamasa Usui , Masami Aoki , Kazuko Yamamoto , Sachiko Kobayashi
IPC分类号： G03F9/00 , G03F1/36 , G03F1/68 , G03F7/00 , G03F7/20 , H01L21/027 , H01L21/768 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G03F7/70425 , G03F1/36 , G03F7/0035
摘要： A method of manufacturing a semiconductor device, comprises the steps of forming a first transfer pattern corresponding to a mask pattern on a major surface side of a semiconductor substrate through a first mask plate on which the first mask pattern having a straight portion and a bent portion is formed, and forming a second transfer pattern corresponding to a second mask pattern on a major surface side of the semiconductor substrate through a second mask plate on which the second mask pattern having a pattern arranged at a position corresponding to the straight portion is formed.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：通过第一掩模板在半导体衬底的主表面侧上形成与掩模图案对应的第一转印图案，其中第一掩模图案具有直的部分和弯曲部分并且通过第二掩模板在半导体衬底的主表面侧上形成与第二掩模图案相对应的第二传输图案，在第二掩模板上形成布置在对应于直线部分的位置处的图案的第二掩模图案。

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