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1. 发明授权

US06110647A Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06110647A
公开(公告)日：2000-08-29
申请号：US024225
申请日：1998-02-17
申请人： Soichi Inoue , Hisashi Kaneko , Masahiko Hasunuma , Takamasa Usui , Masami Aoki , Kazuko Yamamoto , Sachiko Kobayashi
发明人： Soichi Inoue , Hisashi Kaneko , Masahiko Hasunuma , Takamasa Usui , Masami Aoki , Kazuko Yamamoto , Sachiko Kobayashi
IPC分类号： G03F9/00 , G03F1/36 , G03F1/68 , G03F7/00 , G03F7/20 , H01L21/027 , H01L21/768 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G03F7/70425 , G03F1/36 , G03F7/0035
摘要： A method of manufacturing a semiconductor device, comprises the steps of forming a first transfer pattern corresponding to a mask pattern on a major surface side of a semiconductor substrate through a first mask plate on which the first mask pattern having a straight portion and a bent portion is formed, and forming a second transfer pattern corresponding to a second mask pattern on a major surface side of the semiconductor substrate through a second mask plate on which the second mask pattern having a pattern arranged at a position corresponding to the straight portion is formed.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：通过第一掩模板在半导体衬底的主表面侧上形成与掩模图案对应的第一转印图案，其中第一掩模图案具有直的部分和弯曲部分并且通过第二掩模板在半导体衬底的主表面侧上形成与第二掩模图案相对应的第二传输图案，在第二掩模板上形成布置在对应于直线部分的位置处的图案的第二掩模图案。

2. 发明授权

US06946387B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06946387B2
公开(公告)日：2005-09-20
申请号：US10650974
申请日：2003-08-29
申请人： Junichi Wada , Atsuko Sakata , Tomio Katata , Takamasa Usui , Masahiko Hasunuma , Hideki Shibata , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura
发明人： Junichi Wada , Atsuko Sakata , Tomio Katata , Takamasa Usui , Masahiko Hasunuma , Hideki Shibata , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura
IPC分类号： H01L21/285 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76867 , H01L21/2855 , H01L21/76802 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76847 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76859 , H01L21/76864 , H01L21/76877 , H01L21/76879 , H01L21/76886 , H01L21/76889
摘要： A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在具有布线层的Si衬底上形成绝缘膜，形成与布线层连接的接触孔和绝缘膜中的布线槽，用Si 膜，依次在基板上形成Al膜和Ti膜，进行热处理，从而将Al膜替代为Ti膜，并使Si膜被Ti膜吸收，由此填充接触孔和Al膜的布线槽，除去由Ti膜和多余Ti吸收Si膜形成的由Ti硅化物构成的Ti / Ti硅化物，由此用Al塞填充接触孔，并填充布线槽与Al接线。

3. 发明授权

US06673704B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06673704B2
公开(公告)日：2004-01-06
申请号：US10189598
申请日：2002-07-08
申请人： Junichi Wada , Atsuko Sakata , Tomio Katata , Takamasa Usui , Masahiko Hasunuma , Hideki Shibata , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura
发明人： Junichi Wada , Atsuko Sakata , Tomio Katata , Takamasa Usui , Masahiko Hasunuma , Hideki Shibata , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura
IPC分类号： H01L2140
CPC分类号： H01L21/76867 , H01L21/2855 , H01L21/76802 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76847 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76859 , H01L21/76864 , H01L21/76877 , H01L21/76879 , H01L21/76886 , H01L21/76889
摘要： A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在具有布线层的Si衬底上形成绝缘膜，形成与布线层连接的接触孔和绝缘膜中的布线槽，用Si 膜，依次在基板上形成Al膜和Ti膜，进行热处理，从而将Al膜替代为Ti膜，并使Si膜被Ti膜吸收，由此填充接触孔和Al膜的布线槽，除去由Ti膜和多余Ti吸收Si膜形成的由Ti硅化物构成的Ti / Ti硅化物，由此用Al塞填充接触孔，并填充布线槽与Al接线。

4. 发明授权

US06440843B1 Semiconductor device and method for manufacturing the same 失效
公开(公告)号：US06440843B1
公开(公告)日：2002-08-27
申请号：US09556961
申请日：2000-04-21
申请人： Junichi Wada , Atsuko Sakata , Tomio Katata , Takamasa Usui , Masahiko Hasunuma , Hideki Shibata , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura
发明人： Junichi Wada , Atsuko Sakata , Tomio Katata , Takamasa Usui , Masahiko Hasunuma , Hideki Shibata , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura
IPC分类号： H01L2358
CPC分类号： H01L21/76867 , H01L21/2855 , H01L21/76802 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76847 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76859 , H01L21/76864 , H01L21/76877 , H01L21/76879 , H01L21/76886 , H01L21/76889
摘要： A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.

5. 发明授权

US6071810A Method of filling contact holes and wiring grooves of a semiconductor device 失效
标题翻译：填充半导体器件的接触孔和布线槽的方法
公开(公告)号：US6071810A
公开(公告)日：2000-06-06
申请号：US997328
申请日：1997-12-23
申请人： Junichi Wada , Atsuko Sakata , Tomio Katata , Takamasa Usui , Masahiko Hasunuma , Hideki Shibata , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura
发明人： Junichi Wada , Atsuko Sakata , Tomio Katata , Takamasa Usui , Masahiko Hasunuma , Hideki Shibata , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura
IPC分类号： H01L21/285 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76867 , H01L21/2855 , H01L21/76802 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76847 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76859 , H01L21/76864 , H01L21/76877 , H01L21/76879 , H01L21/76886 , H01L21/76889
摘要： A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在具有布线层的Si衬底上形成绝缘膜，形成与布线层连接的接触孔和绝缘膜中的布线槽，用Si 膜，依次在基板上形成Al膜和Ti膜，进行热处理，从而将Al膜替代为Ti膜，并使Si膜被Ti膜吸收，由此填充接触孔和Al膜的布线槽，除去由Ti膜和多余Ti吸收Si膜形成的由Ti硅化物构成的Ti / Ti硅化物，由此用Al塞填充接触孔，并填充布线槽与Al接线。

6. 发明授权

US07635646B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07635646B2
公开(公告)日：2009-12-22
申请号：US12128789
申请日：2008-05-29
申请人： Seiichi Omoto , Hisashi Kaneko , Masahiko Hasunuma
发明人： Seiichi Omoto , Hisashi Kaneko , Masahiko Hasunuma
IPC分类号： H01L21/44
CPC分类号： H01L21/76852 , H01L21/7682 , H01L21/76834 , H01L21/76885 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device, includes forming a first dielectric film above a substrate, forming an opening in the first dielectric film, forming a catalytic characteristic film using at least one of a metal having catalytic characteristics and a conductive oxide having catalytic characteristics as its material on sidewalls and at a bottom of the opening, depositing a conductive material film using a conductive material in the opening in which the catalytic characteristic film is formed on the sidewalls and at the bottom, removing the catalytic characteristic film formed on the sidewalls of the opening, and forming a second dielectric film above the first dielectric film and the conductive material film after the removing.
摘要翻译：一种制造半导体器件的方法，包括在衬底上形成第一电介质膜，在第一介电膜中形成开口，使用具有催化特性的金属和具有催化特性的导电氧化物中的至少一种形成催化特性膜，其材料在侧壁和开口的底部，在开口中使用导电材料沉积导电材料膜，在该开口中，在侧壁和底部形成催化特征膜，除去形成在侧壁上的催化特性膜并且在去除之后在第一电介质膜和导电材料膜之上形成第二电介质膜。

7. 发明授权

US07601638B2 Interconnect metallization method having thermally treated copper plate film with reduced micro-voids 有权
标题翻译：具有经热处理的铜版薄膜与微孔减少的互连金属化方法
公开(公告)号：US07601638B2
公开(公告)日：2009-10-13
申请号：US11926614
申请日：2007-10-29
申请人： Masahiko Hasunuma , Hisashi Kaneko , Hiroshi Toyoda
发明人： Masahiko Hasunuma , Hisashi Kaneko , Hiroshi Toyoda
IPC分类号： H01L21/4763
CPC分类号： H01L21/76877 , C23C26/00 , C25D5/02 , C25D5/18 , C25D5/50 , C25D7/123 , H01L21/2885
摘要： A method for manufacturing a semiconductor device includes forming, on a substrate having a recessed portion on a surface, a plating film which is at least buried in the recessed portion and has a higher impurity concentration in an upper portion than in a lower portion, thermally treating the plating film, and removing the thermally treated plating film except for a portion buried in the recessed portion.
摘要翻译：一种半导体器件的制造方法，其特征在于，在具有表面的凹部的基板上形成至少埋设在所述凹部内并且在上部比在下部具有较高的杂质浓度的镀膜处理镀膜，除去除了凹部中的部分以外的热处理电镀膜。

8. 发明申请

US20080299766A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20080299766A1
公开(公告)日：2008-12-04
申请号：US12128789
申请日：2008-05-29
申请人： Seiichi OMOTO , Hisashi Kaneko , Masahiko Hasunuma
发明人： Seiichi OMOTO , Hisashi Kaneko , Masahiko Hasunuma
IPC分类号： H01L21/44
CPC分类号： H01L21/76852 , H01L21/7682 , H01L21/76834 , H01L21/76885 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device, includes forming a first dielectric film above a substrate, forming an opening in the first dielectric film, forming a catalytic characteristic film using at least one of a metal having catalytic characteristics and a conductive oxide having catalytic characteristics as its material on sidewalls and at a bottom of the opening, depositing a conductive material film using a conductive material in the opening in which the catalytic characteristic film is formed on the sidewalls and at the bottom, removing the catalytic characteristic film formed on the sidewalls of the opening, and forming a second dielectric film above the first dielectric film and the conductive material film after the removing.
摘要翻译：一种制造半导体器件的方法，包括在衬底上形成第一电介质膜，在第一介电膜中形成开口，使用具有催化特性的金属和具有催化特性的导电氧化物中的至少一种形成催化特性膜，其材料在侧壁和开口的底部，在开口中使用导电材料沉积导电材料膜，在该开口中，在侧壁和底部形成催化特征膜，除去形成在侧壁上的催化特性膜并且在去除之后在第一电介质膜和导电材料膜之上形成第二电介质膜。

9. 发明授权

US06001461A Electronic parts and manufacturing method thereof 失效
标题翻译：电子零件及其制造方法
公开(公告)号：US06001461A
公开(公告)日：1999-12-14
申请号：US771388
申请日：1996-12-19
申请人： Hiroshi Toyoda , Hisashi Kaneko , Masahiko Hasunuma , Takashi Kawanoue , Hiroshi Tomita , Akihiro Kajita , Masami Miyauchi , Takashi Kawakubo , Sachiyo Ito
发明人： Hiroshi Toyoda , Hisashi Kaneko , Masahiko Hasunuma , Takashi Kawanoue , Hiroshi Tomita , Akihiro Kajita , Masami Miyauchi , Takashi Kawakubo , Sachiyo Ito
IPC分类号： H01L21/3205 , H01L23/528 , H01L23/532 , B32B9/00
CPC分类号： H01L23/532 , H01L21/32051 , H01L23/5283 , H01L23/53223 , H01L2924/0002 , Y10T428/2457 , Y10T428/24926
摘要： An electronic part comprising an amorphous thin film formed on a substrate; and a metal wiring formed on the surface of the amorphous thin film; wherein an interatomic distance corresponding to a peak of halo pattern appearing in diffraction measurement of the amorphous thin film approximately matches with a spacing of a particular crystal plane defined with the first nearest interatomic distance of the metal wiring. An electronic part provided with a metal wiring formed of highly orientated crystal wherein half or more of all grain boundaries are small angle grain boundaries defined by one of grain boundaries with a relative misorientation of 10.degree. or less in tilt, rotation and combination thereof around orientation axes of neighboring crystal grains; coincidence boundaries where a .SIGMA. value is 10 or less; and grain boundaries with a relative misorientation of 3.degree. or less from the coincidence boundary. A method for manufacturing an electronic part, comprising the step of depositing a conductor layer which is mainly formed of one selected from Al and Cu on a substrate via an insulative layer, a barrier layer, a contact layer or an amorphous thin film layer wherein one element selected from Ga, In, Cd, Bi, Pb, Sn and Tl is supplied before or during the deposition of the conductor layer.
摘要翻译：一种电子部件，包括形成在基板上的非晶薄膜; 以及形成在所述非晶薄膜的表面上的金属布线; 其中对应于在非晶薄膜的衍射测量中出现的晕轮图案的峰值的原子间距离大致与由金属布线的第一最接近的原子间距离限定的特定晶面的间隔相匹配。一种电子部件，其具有由高取向晶体形成的金属布线，其中所有晶界的一半以上是由倾斜，旋转及其组合在取向方向上的相位差取向为10°以下的晶界之一限定的小角度晶界相邻晶粒的轴; SIGMA值为10以下的重合边界; 晶界与重合边界的相对误差为3°以下。一种电子部件的制造方法，其特征在于，包括以下步骤：通过绝缘层，阻挡层，接触层或无定形薄膜层，在基板上沉积主要由选自Al和Cu的一个导体层形成的步骤，其中一个选自Ga，In，Cd，Bi，Pb，Sn和Tl的元素在导体层的沉积之前或期间提供。

10. 发明授权

US5709958A Electronic parts 失效
标题翻译：电子零件
公开(公告)号：US5709958A
公开(公告)日：1998-01-20
申请号：US451528
申请日：1995-05-26
申请人： Hiroshi Toyoda , Hisashi Kaneko , Masahiko Hasunuma , Takashi Kawanoue , Hiroshi Tomita , Akihiro Kajita , Masami Miyauchi , Takashi Kawakubo , Sachiyo Ito
发明人： Hiroshi Toyoda , Hisashi Kaneko , Masahiko Hasunuma , Takashi Kawanoue , Hiroshi Tomita , Akihiro Kajita , Masami Miyauchi , Takashi Kawakubo , Sachiyo Ito
IPC分类号： H01L21/3205 , H01L23/528 , H01L23/532 , H01L29/43
CPC分类号： H01L21/32051 , H01L23/5283 , H01L23/532 , H01L23/53223 , H01L2924/0002 , Y10T428/12528 , Y10T428/12674 , Y10T428/12681
摘要： An electronic part comprising an amorphous thin film formed on a substrate; and a metal wiring formed on the surface of the amorphous thin film; wherein an interatomic distance corresponding to a peak of halo pattern appearing in diffraction measurement of the amorphous thin film approximately matches with a spacing of a particular crystal plane defined with the first nearest interatomic distance of the metal wiring. An electronic part provided with a metal wiring formed of highly orientated crystal wherein half or more of all grain boundaries are small angle grain boundaries defined by one of grain boundaries with a relative misorientation of 10.degree. or less in tilt, rotation and combination thereof around orientation axes of neighboring crystal grains; coincidence boundaries where a .SIGMA. value is 10 or less; and grain boundaries with a relative misorientation of 3.degree. or less from the coincidence boundary. A method for manufacturing an electronic part, comprising the step of depositing a conductor layer which is mainly formed of one selected from Al and Cu on a substrate via an insulative layer, a barrier layer, a contact layer or an amorphous thin film layer wherein one element selected from Ga, In, Cd, Bi, Pb, Sn and Tl is supplied before or during the deposition of the conductor layer.
摘要翻译：一种电子部件，包括形成在基板上的非晶薄膜; 以及形成在所述非晶薄膜的表面上的金属布线; 其中对应于在非晶薄膜的衍射测量中出现的晕轮图案的峰值的原子间距离大致与由金属布线的第一最接近的原子间距离限定的特定晶面的间隔相匹配。一种电子部件，其具有由高取向晶体形成的金属布线，其中所有晶界的一半以上是由倾斜，旋转及其组合在取向方向上的相位差取向为10°以下的晶界之一限定的小角度晶界相邻晶粒的轴; SIGMA值为10以下的重合边界; 晶界与重合边界的相对误差为3°以下。一种电子部件的制造方法，其特征在于，包括以下步骤：通过绝缘层，阻挡层，接触层或无定形薄膜层，在基板上沉积主要由选自Al和Cu的一个导体层形成的步骤，其中一个选自Ga，In，Cd，Bi，Pb，Sn和Tl的元素在导体层的沉积之前或期间提供。

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