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81. 发明授权

US07558108B2 3-bit NROM flash and method of operating same 有权
标题翻译： 3位NROM闪存和操作方法相同
公开(公告)号：US07558108B2
公开(公告)日：2009-07-07
申请号：US11265767
申请日：2005-11-01
申请人： Noam Eshel
发明人： Noam Eshel
IPC分类号： G11C11/34
CPC分类号： G11C11/5671 , G11C16/0475
摘要： Operation of conventional nitride read-only-memory (NROM) cells is modified, such that each charge trapping region of an NROM cell is capable of storing any one of three charge states. For example, each charge trapping region can have an erased state, a first programmed state, or a second programmed state. Each of these states results in a different threshold voltage. During a read operation, the threshold voltages associated with two charge trapping regions are identified and decoded to provide a 3-bit data value. If each NROM cell includes two separate charge trapping regions, two NROM cells can store a total of 6-bits of data. The average storage density is therefore increased from two bits per NROM cell to three bits per NROM cell.
摘要翻译：修改常规氮化物只读存储器（NROM）单元的操作，使得NROM单元的每个电荷捕获区域能够存储三种电荷状态中的任何一种。例如，每个电荷捕获区域可以具有擦除状态，第一编程状态或第二编程状态。这些状态中的每一个导致不同的阈值电压。在读取操作期间，识别和解码与两个电荷俘获区域相关联的阈值电压以提供3位数据值。如果每个NROM单元包括两个单独的电荷俘获区域，则两个NROM单元可以存储总共6位的数据。因此，平均存储密度从每个NROM单元的两位增加到每个NROM单元的三位。

82. 发明授权

US07482233B2 Embedded non-volatile memory cell with charge-trapping sidewall spacers 有权
标题翻译：嵌入式非易失性存储单元，具有电荷陷阱侧壁间隔
公开(公告)号：US07482233B2
公开(公告)日：2009-01-27
申请号：US11753493
申请日：2007-05-24
申请人： Yakov Roizin , Amos Fenigstein
发明人： Yakov Roizin , Amos Fenigstein
IPC分类号： H01L21/8234
CPC分类号： G11C16/0475 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/11526 , H01L27/11534 , H01L27/11568
摘要： An IC includes both “volatile” CMOS transistors (FETs) and embedded non-volatile memory (NVM) cells, both including polysilicon gate structures, sidewall oxide layers, sidewall spacer structures, and source/drain regions. The sidewall spacers of both the NVM cells and the FETs are made up of a spacer material with local charge storage nodes that is capable of storing electrical charge (e.g., silicon-nitride with traps or oxide with silicon nanocrystals). The source/drain regions of the NVM cells omit lightly-doped drains (which are used in the CMOS FETs), and the NVM cells are formed with thinner sidewall oxide layers than the CMOS FETs to facilitate programming/erasing operations. A production method includes a modified CMOS process flow where the CMOS FET gate structures receive different source/drain diffusions and oxides than the NVM gate structures, but both receive substantially identical sidewall spacers, which are used as charge storage structures in the NVM cells.
摘要翻译： IC包括“易失性”CMOS晶体管（FET）和嵌入式非易失性存储器（NVM）单元，两者都包括多晶硅栅极结构，侧壁氧化物层，侧壁间隔结构和源极/漏极区域。 NVM单元和FET的侧壁间隔物由具有能够存储电荷的局部电荷存储节点（例如具有陷阱的氮化硅或具有硅纳米晶体的氧化物的氮化硅）的间隔物材料构成。 NVM单元的源极/漏极区域省略了轻掺杂漏极（其用于CMOS FET），并且NVM单元形成有比CMOS FET更薄的侧壁氧化物层，以便于编程/擦除操作。制造方法包括改进的CMOS工艺流程，其中CMOS FET栅极结构接收不同于NVM栅极结构的不同的源极/漏极扩散和氧化物，但都接收基本上相同的侧壁间隔物，其用作NVM单元中的电荷存储结构。

83. 发明申请

US20060255398A1 Ultra-violet protected tamper resistant embedded EEPROM 审中-公开
标题翻译：紫外线防篡改嵌入式EEPROM
公开(公告)号：US20060255398A1
公开(公告)日：2006-11-16
申请号：US11338418
申请日：2006-01-23
申请人： Yakov Roizin , Yosi Netzer , Ira Naot , Myriam Buchbinder , Avi Ben-Guigui
发明人： Yakov Roizin , Yosi Netzer , Ira Naot , Myriam Buchbinder , Avi Ben-Guigui
IPC分类号： H01L29/792
CPC分类号： H01L23/552 , H01L23/585 , H01L27/115 , H01L27/11521 , H01L27/11558 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A pre-metal dielectric structure of a single-poly EEPROM structure includes a UV light-absorbing film, which prevents the charge on a floating gate of the EEPROM structure from being changed in response to UV radiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer, an amorphous silicon layer located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the amorphous silicon layer.
摘要翻译：单聚电解质EEPROM结构的预金属电介质结构包括UV光吸收膜，其防止EEPROM结构的浮动栅极上的电荷响应于紫外线辐射而改变。在一个实施例中，前金属介电结构包括第一预金属电介质层，位于第一预金属介电层上方的非晶硅层和位于非晶硅层之上的第二预金属介电层。

84. 发明申请

US20060094257A1 Low thermal budget dielectric stack for SONOS nonvolatile memories 审中-公开
标题翻译：用于SONOS非易失性存储器的低热量预算介质堆叠
公开(公告)号：US20060094257A1
公开(公告)日：2006-05-04
申请号：US11267928
申请日：2005-11-03
申请人： Alon Hoffman , Rachel Edrei , Meirav Saraf , Yakov Roizin , Ruth Shima-Edelstein
发明人： Alon Hoffman , Rachel Edrei , Meirav Saraf , Yakov Roizin , Ruth Shima-Edelstein
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L29/518 , G11C16/0475 , H01L21/02164 , H01L21/0217 , H01L21/02175 , H01L21/02271 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L29/40114 , H01L29/513
摘要： A method of forming an oxide-nitride-oxide (ONO) structure for use in a non-volatile memory cell, which includes (1) forming a first oxide layer over a substrate, (2) forming a silicon nitride layer over the first oxide layer, (3) introducing oxygen into a top interface of the silicon nitride layer, and then (4) forming a second oxide layer over the silicon nitride layer.
摘要翻译：一种形成用于非易失性存储单元的氧化物 - 氧化物（ONO）结构的方法，其包括：（1）在衬底上形成第一氧化物层，（2）在所述第一氧化物上形成氮化硅层（3）将氧气引入到氮化硅层的顶部界面中，然后（4）在氮化硅层上形成第二氧化物层。

85. 发明授权

US06956771B2 Voltage control circuit for high voltage supply 失效
标题翻译：高压电源电压控制电路
公开(公告)号：US06956771B2
公开(公告)日：2005-10-18
申请号：US10228452
申请日：2002-08-26
申请人： Erez Sarig , Ran Rosenweig
发明人： Erez Sarig , Ran Rosenweig
IPC分类号： G11C16/30 , H01L27/02 , H01L29/06 , G11C16/00
CPC分类号： G11C16/30 , H01L27/0222 , H01L29/0615 , Y10T307/826
摘要： A voltage control circuit that utilizes a level-shifter circuit and a switch circuit to isolate a charge pump output terminal from a system voltage source when a charge pump is enabled, and to couple the charge pump output terminal to the system voltage source when the charge pump is disabled. The level-shifter circuit receives the charge pump output voltage as its high voltage supply and the charge pump enable signal as its input signal, and transmits the charge pump output voltage from its output terminal when the charge pump is enabled, and zero volts when the charge pump is disabled. The switch circuit includes a PMOS transistor constructed such that its bulk and source are connected to the charge pump output terminal, and its drain is connected to the system voltage source. The switch circuit also includes a guard ring structure surrounding the PMOS transistor.
摘要翻译：一种电压控制电路，其在电荷泵使能时利用电平转换电路和开关电路将电荷泵输出端子与系统电压源隔离，并且当充电时将电荷泵输出端子耦合到系统电压源泵被禁用。电平转换电路将电荷泵输出电压作为其高电压电源和电荷泵使能信号作为其输入信号，当电荷泵使能时，从其输出端子发送电荷泵输出电压，当电荷泵输出电压为零时电荷泵被禁用。开关电路包括PMOS晶体管，其构造使得其体积和源极连接到电荷泵输出端，并且其漏极连接到系统电压源。开关电路还包括围绕PMOS晶体管的保护环结构。

86. 发明申请

US20050186741A1 SONOS embedded memory with CVD dielectric 失效
标题翻译： SONOS嵌入式存储器，采用CVD电介质
公开(公告)号：US20050186741A1
公开(公告)日：2005-08-25
申请号：US10783466
申请日：2004-02-20
申请人： Yakov Roizin , Zmira Shterenfeld-Lavie , Itzhak Edrei
发明人： Yakov Roizin , Zmira Shterenfeld-Lavie , Itzhak Edrei
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/8239 , H01L21/8246 , H01L21/8247 , H01L27/105
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/1052 , H01L27/11521 , H01L27/11573
摘要： An embedded semiconductor memory is fabricated by: forming diffusion bit line regions in a semiconductor substrate; then thermally oxidizing the upper surface of the substrate, thereby forming a bottom oxide layer over the substrate and simultaneously forming bit line oxide regions over each of the diffusion bit line regions; and then forming an intermediate dielectric layer (e.g., silicon nitride), over the bottom oxide layer and the bit line oxide regions. CMOS well implants are then performed in a CMOS section of the device through the silicon nitride layer and bottom oxide layer. The silicon nitride layer and bottom oxide layer are then removed in the CMOS section, and a top dielectric layer, such as a high-temperature oxide or a high-k dielectric, is deposited. The top dielectric layer completes a memory stack of the memory device, and forms a gate dielectric layer of a high voltage transistor in the CMOS section.
摘要翻译：通过在半导体衬底中形成扩散位线区域来制造嵌入式半导体存储器; 然后热氧化衬底的上表面，从而在衬底上形成底部氧化物层，同时在每个扩散位线区域上形成位线氧化物区域; 然后在底部氧化物层和位线氧化物区域上形成中间介电层（例如，氮化硅）。然后通过氮化硅层和底部氧化物层在器件的CMOS部分中执行CMOS阱注入。然后在CMOS部分中去除氮化硅层和底部氧化物层，并且沉积顶部电介质层，例如高温氧化物或高k电介质。顶部介电层完成存储器件的存储器堆叠，并在CMOS部分中形成高压晶体管的栅极电介质层。

87. 发明申请

US20050088878A1 NEIGHBOR EFFECT CANCELLATION IN MEMORY ARRAY ARCHITECTURE 失效
标题翻译：邻域效应在存储阵列架构中的消除
公开(公告)号：US20050088878A1
公开(公告)日：2005-04-28
申请号：US10696728
申请日：2003-10-27
申请人： Noam Eshel
发明人： Noam Eshel
IPC分类号： G11C16/28 , G11C11/34
CPC分类号： G11C16/28
摘要： Non-volatile memory (NVM) cells are sensed using a forced neighbor signal to eliminate improper readings generated by a neighbor effect. A selected NVM cell is sensed using a near-ground signal by applying a potential to a first terminal, coupling a second terminal to ground, and then decoupling the second terminal and comparing the resulting cell signal with a reference signal as both signals are developing (i.e., increasing from ground). A forced neighbor signal is applied to one more neighboring cells such that as the sensed cell signal develops (increases from ground), the forced neighbor signal develops at a similar rate, thereby maintaining a voltage across the neighboring cells close to zero and thus preventing leakage of the sensed cell signal through the neighbor cell(s). A dc sensing approach utilizes a current source and grounded resistor to minimize leakage through the neighbor cell(s).
摘要翻译：使用强制相邻信号感测非易失性存储器（NVM）单元，以消除由相邻效应产生的不正确读取。使用近地信号，通过向第一终端施加电位，将第二端耦合到地，然后将第二端耦合并在两个信号正在展开时将所得到的信号与参考信号进行比较，来使用近地信号来感测选定的NVM单元即从地面增加）。强制相邻信号被施加到一个更邻近的小区，使得随着感测到的小区信号的发展（从地面增加），强制邻居信号以相似的速率发展，从而保持邻近小区的电压接近零，从而防止泄漏的感测单元信号通过相邻单元。直流感测方法利用电流源和接地电阻来最小化通过相邻电池的泄漏。

88. 发明申请

US20050003659A1 Transparent inter-metal dielectric stack for CMOS image sensors 审中-公开
标题翻译：用于CMOS图像传感器的透明金属间介质堆叠
公开(公告)号：US20050003659A1
公开(公告)日：2005-01-06
申请号：US10613849
申请日：2003-07-03
申请人： Leah Markowitz , Roey Shaviv
发明人： Leah Markowitz , Roey Shaviv
IPC分类号： H01L21/4763 , H01L27/146
CPC分类号： H01L27/14636 , H01L27/14621 , H01L27/14643
摘要： A transparent inter-metal dielectric utilized in a CMOS image sensor includes a flowlayer sandwiched between a base SiO2 layer and a cap SiO2 layer. The flowlayer is formed by reacting SiH4 and H2O2 using a shortened H2O2 stabilization time, using a reduced deposition pressure, and while maintaining the reaction chamber platen at a target value of approximately 1° C.
摘要翻译：在CMOS图像传感器中使用的透明金属间电介质包括夹在基底SiO 2层和帽状SiO 2层之间的流层。流层通过使用缩短的H 2 O 2稳定时间，使用降低的沉积压力，同时将反应室压板保持在约1℃的目标值，使SiH 4和H 2 O 2反应而形成。

89. 发明申请

US20040100822A1 FOUR-BIT NON-VOLATILE MEMORY TRANSISTOR AND ARRAY 失效
标题翻译：四位非易失性存储器晶体管和阵列
公开(公告)号：US20040100822A1
公开(公告)日：2004-05-27
申请号：US10305403
申请日：2002-11-26
申请人： Tower Semiconductor Ltd.
发明人： Yakov Roizin , Micha Gutman , Shimon Greenberg , Alfred Yankelevich
IPC分类号： G11C016/04
CPC分类号： G11C16/0475 , H01L27/115 , H01L29/7923
摘要： A non-volatile memory cell capable of storing more than two bits of information. The NVM cell includes a semiconductor region having a first conductivity type, and a plurality of field isolation regions located in the semiconductor region. Four or more source/drain regions are located in the semiconductor region adjacent to the field isolation regions, the source/drain regions having a second conductivity type, opposite the first conductivity type. The field isolation regions and the source drain regions laterally surround a channel region in the semiconductor region. A gate structure, including a floating gate structure and a control gate structure, extends over the channel region, portions of the field isolation regions and portions of the source/drain regions. The floating gate structure includes a plurality of charge trapping regions, wherein each of the charge trapping regions is located adjacent to a corresponding one of the source/drain regions.
摘要翻译：能够存储多于两位信息的非易失性存储单元。 NVM单元包括具有第一导电类型的半导体区域和位于半导体区域中的多个场隔离区域。四个或更多个源极/漏极区域位于与场隔离区域相邻的半导体区域中，源极/漏极区域具有与第一导电类型相反的第二导电类型。场隔离区域和源漏区域横向地围绕半导体区域中的沟道区域。包括浮置栅极结构和控制栅极结构的栅极结构在沟道区域，场隔离区的部分和源极/漏极区的部分之间延伸。浮置栅极结构包括多个电荷俘获区域，其中每个电荷俘获区域位于与源极/漏极区域中相应的一个相邻的位置。

90. 发明授权

US6044022A Programmable configuration for EEPROMS including 2-bit non-volatile memory cell arrays 有权
标题翻译：包括2位非易失性存储单元阵列的EEPROMS的可编程配置
公开(公告)号：US6044022A
公开(公告)日：2000-03-28
申请号：US258059
申请日：1999-02-26
申请人： Ishai Nachumovsky
发明人： Ishai Nachumovsky
IPC分类号： G11C11/56 , G11C16/04 , G11C16/26
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/26 , G11C19/00 , G11C2211/5641 , G11C8/04
摘要： A structure and method for configuring an EEPROM having an array of 2-bit non-volatile memory transistors to perform either in a high-speed 1-bit operation mode or a high-density 2-bit operation mode. Each memory transistor has a first charge trapping region for storing a first bit and a second charge trapping region for storing a second bit. The selected operation mode is determined by configuration data set by the EEPROM manufacturer in accordance with a customer's requirements. In one embodiment, an EEPROM includes blocks of memory cells accessed by a single word line. When the configuration data indicates the 1-bit operation mode, the memory control circuit stores data in only one of the two charge trapping regions of each memory cell. All eight bits of a word are read simultaneously by accessing eight separate charge trapping regions. Conversely, when the configuration data indicates the 2-bit operation mode, the memory control circuit stores data in both charge trapping regions of each memory cell. A read operation in the 2-bit operation mode requires reading a first group of four bits during a first stage, and then reading a second group of four bits during a second stage. These first and second groups of bits are successively stored in a shift register, and then transmitted to an I/O control circuit.
摘要翻译：一种用于配置具有2位非易失性存储晶体管阵列的EEPROM以在高速1位操作模式或高密度2位操作模式中执行的结构和方法。每个存储晶体管具有用于存储第一位的第一电荷俘获区和用于存储第二位的第二电荷捕获区。所选择的操作模式由EEPROM制造商根据客户要求设置的配置数据确定。在一个实施例中，EEPROM包括由单个字线访问的存储器单元的块。当配置数据指示1位操作模式时，存储器控制电路仅将数据存储在每个存储器单元的两个电荷捕获区域中的一个中。通过访问八个单独的电荷捕获区域，一个字的所有8位同时读取。相反，当配置数据指示2位操作模式时，存储器控制电路将数据存储在每个存储单元的两个电荷捕获区域中。在2位操作模式下的读取操作需要在第一级期间读取第一组四位，然后在第二级期间读取第二组四位。这些第一和第二组比特连续存储在移位寄存器中，然后发送到I / O控制电路。

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